GX1 Datasheet, PDF (231/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Instruction Set (Continued)
Table 8-27. Processor Core Instruction Set Summary (Continued)
Flags
Real Prot’d Real Prot’d
Mode Mode Mode Mode
Instruction
Opcode
SETNB/SETAE/SETNC Set Byte on Not Below/Above or Equal/Not Carry
To Register/Memory
0F 93 [mod 000 r/m]
SETNBE/SETA Set Byte on Not Below or Equal/Above
To Register/Memory
0F 97 [mod 000 r/m]
SETNE/SETNZ Set Byte on Not Equal/Not Zero
To Register/Memory
0F 95 [mod 000 r/m]
SETNL/SETGE Set Byte on Not Less/Greater or Equal
To Register/Memory
0F 9D [mod 000 r/m]
SETNLE/SETG Set Byte on Not Less or Equal/Greater
To Register/Memory
0F 9F [mod 000 r/m]
SETNO Set Byte on Not Overflow
To Register/Memory
0F 91 [mod 000 r/m]
SETNP/SETPO Set Byte on Not Parity/Parity Odd
To Register/Memory
0F 9B [mod 000 r/m]
SETNS Set Byte on Not Sign
To Register/Memory
0F 99 [mod 000 r/m]
SETO Set Byte on Overflow
To Register/Memory
0F 90 [mod 000 r/m]
SETP/SETPE Set Byte on Parity/Parity Even
To Register/Memory
0F 9A [mod 000 r/m]
SETS Set Byte on Sign
To Register/Memory
0F 98 [mod 000 r/m]
SGDT Store GDT Register
To Register/Memory
0F 01 [mod 000 r/m]
SIDT Store IDT Register
To Register/Memory
0F 01 [mod 001 r/m]
SLDT Store LDT Register
To Register/Memory
0F 00 [mod 000 r/m]
STR Store Task Register
To Register/Memory
0F 00 [mod 001 r/m]
SMSW Store Machine Status Word
0F 01 [mod 100 r/m]
STOS Store String
A [101w]
SHL Shift Left Logical
Register/Memory by 1
D [000w] [mod 100 r/m]
Register/Memory by CL
D [001w] [mod 100 r/m]
Register/Memory by Immediate
C [000w] [mod 100 r/m] #
SHLD Shift Left Double
Register/Memory by Immediate
0F A4 [mod reg r/m] #
Register/Memory by CL
0F A5 [mod reg r/m]
SHR Shift Right Logical
Register/Memory by 1
D [000w] [mod 101 r/m]
Register/Memory by CL
D [001w] [mod 101 r/m]
Register/Memory by Immediate
C [000w] [mod 101 r/m] #
SHRD Shift Right Double
Register/Memory by Immediate
0F AC [mod reg r/m] #
Register/Memory by CL
0F AD [mod reg r/m]
SMINT Software SMM Entry
0F 38
STC Set Carry Flag
F9
STD Set Direction Flag
FD
STI Set Interrupt Flag
FB
O D I T S Z A P C Clock Count
F F F F F F F F F (Reg/Cache Hit)
Issues
---------
1
---------
1
---------
1
---------
1
---------
1
---------
1
---------
1
---------
1
---------
1
---------
1
---------
1
---------
6
---------
6
---------
---------
---------
4
---------
2
x- - - xxuxx
1
u- - - xxuxx
2
u- - - xxuxx
1
u- - - xxuxx
3
6
x- - - xxuxx
2
u- - - xxuxx
2
u- - - xxuxx
2
u- - - xxuxx
3
6
---------
84
--------1
1
- 1- - - - - - -
4
- - 1- - - - - -
6
1
h
1
h
1
h
1
h
1
h
1
h
1
h
1
h
1
h
1
h
1
h
6
b,c
h
6
b,c
h
1
a
h
3
a
h
4
b,c
h
2
b
h
1
b
h
2
1
3
b
h
6
2
b
h
2
2
3
b
h
6
84
s
s
1
4
6
m
Revision 1.0
231
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