GX1 Datasheet, PDF (100/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Integrated Functions (Continued)
4.1.4 Scratchpad RAM
To improve software performance for specific applications,
part of the L1 cache (2, 3, or 4 KB) can be programmed to
operate as a scratchpad RAM. This scratchpad RAM oper-
ates at L1 speed which can speed up time-critical software
operations. The scratchpad RAM is taken from set 0 of the
L1 cache. Setting aside this RAM makes the L1 cache
smaller by the scratchpad RAM size. The scratchpad RAM
size is controlled by bits in the GCR register (Index B8h,
bits[3:2]). See Table 4-1 on page 97.
The scratchpad RAM is usually memory mapped by BIOS
to the upper memory region defined by the GCR register
(Index B8h, bits [1:0]). Once enabled, the valid bits for the
scratchpad RAM will always be true and the scratchpad
RAM locations will never be flushed to external memory.
The scratchpad RAM serves as a general purpose high
speed RAM and as a BLT buffer for the graphics pipeline.
4.1.4.1 Initialization of Scratchpad RAM
The scratchpad RAM must be initialized before the L1
cache is enabled. To initialize the scratchpad RAM after a
cold boot:
1) Initialize the tags of the scratchpad RAM using the test
registers TR4 and TR5 as outlined in Section 3.3.2.5
“Cache Test Registers” on page 59. The tags are
normally programmed with an address value equiva-
lent to GX_BASE (GCR register).
2) Enable the scratchpad RAM to the desired size (GCR
register). This action will also lock down the tags.
3) Enable the L1 cache. See Section 3.3.2.1 “Control
Registers” on page 48.
4.1.4.2 Scratchpad RAM Utilization
Use of scratchpad RAM by applications and drivers must
be tightly controlled. To avoid conflicts, application software
and third-party drivers should generally avoid accesses to
the scratchpad RAM area. The scratchpad RAM is used by
the graphics pipeline BLT buffers, and National supplied
display drivers and virtualization software. Table 4-3
describes the 2 KB, 3 KB, and 4 KB scratchpad RAM orga-
nization used by National developed software. The BLT
buffers are programmed using CPU_READ/CPU_WRITE
instructions described in Section 4.1.6 on page 102. If the
graphics pipeline or National software is used, and it is
desirable to use scratchpad RAM by software other than
that supplied by National, please contact your local
National Semiconductor technical support representative.
4.1.4.3 BLT Buffer
Address registers, BitBLT, have been added to the front
end of the L1 cache to enable the graphics pipeline to
directly access a portion of the scratchpad RAM as a BLT
buffer. Table 4-4 summarizes these registers. These regis-
ters do not have default values and must be initialized
before use. Table 4-5 gives the register/bit formats. A 16-
byte line buffer dedicated to the graphics pipeline BLT oper-
ations has been added to minimize accesses to the L1
cache.
When the BLT operation begins, the graphics pipeline gen-
erates a 32 bit data BLT request to the L1 cache. This
request goes through the BitBLT registers to produce an
address into the scratchpad RAM. The L1_BBx_POINTER
register automatically increments after each access. A BLT
operation generates many accesses to the BLT buffer to
complete a BLT transfer. At the end of the BLT operation
the graphics pipeline generates a signal to reload the
L1_BBx_POINTER register with the L1_BBx_BASE regis-
ter. This allows the BLT buffer to be used over and over
again with a minimum of software overhead.
See Section 4.4 “Graphics Pipeline” on page 125 on pro-
gramming the graphics pipeline to generate a BLT.
2 KB Configuration
Offset
GX_BASE + 0EE0h
GX_BASE + 0E60h
GX_BASE + 0800h
GX_BASE + 0B30h
Size
288 bytes
128 bytes
816 bytes
816 bytes
Table 4-3. Scratchpad Organization
3 KB Configuration
4 KB Configuration
Offset
GX_BASE + 0EE0h
GX_BASE + 0E60h
GX_BASE + 0400h
GX_BASE + 0930h
Size
288 bytes
128 bytes
1328 bytes
1328 bytes
Offset
GX_BASE + 0EE0h
GX_BASE + 0E60h
GX_BASE + 0h
GX_BASE + 730h
Size
288 bytes
128 bytes
1840 bytes
1840 bytes
Description
SMM scratchpad
Driver scratchpad
BLT Buffer 0
BLT Buffer 1
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