GX1 Datasheet, PDF (162/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Integrated Functions (Continued)
The ALU is a simple two-operand ROP unit that operates
on writes. Its operating modes are COPY, AND, OR, and
XOR. The 32-bit inputs are:
1) the output of the write-mode unit and
2) the display latch (not necessarily the value at the
frame buffer address of the write).
An application that wishes to perform ROPs on the source
and destination must first byte read the address (to load
the latch) and then immediately write a byte to the same
address. The ALU has no effect in Write Mode 1.
The bit mask unit does not provide a true bit mask. Instead,
it selects between the ALU output and the display latch.
The mask is an 8-bit value, and bit n of the mask makes the
selection for bit n of all four bytes of the result (a zero
selects the latch). No bit masking occurs in Write Mode 1.
The VGA hardware of the GX1 processor does not imple-
ment Write Mode 1 directly, but it can be indirectly imple-
mented by setting the BitMask to zero and the ALU mode
to COPY. This is done by the SMM code so there are no
compatibility issues with applications.
4.6.2.2 GX1 VGA Hardware
The GX1 processor core contains hardware to detect VGA
accesses and generate SMI interrupts. The graphics pipe-
line contains hardware to detect and process reads and
writes to VGA memory. The VGA memory on the GX1 pro-
cessor is partitioned from system memory. The GX1 pro-
cessor has the following hardware components to assist
the VGA emulation software.
• SMI Generation
• VGA Range Detection
• VGA Sequencer
• VGA Write/Read Path
• VGA Address Generator
• VGA Memory
4.6.2.3 SMI Generation
VGA emulation software is notified of VGA memory
accesses by an SMI generated in dedicated circuitry in the
processor core that detects and traps memory accesses.
The SMI generation hardware for VGA memory addresses
is in the second stage of instruction decoding on the pro-
cessor core. This is the earliest stage of instruction decode
where virtual addresses have been translated to physical
addresses. Trapping after the execution stage is impracti-
cal, because memory write buffering will allow subsequent
instructions to execute.
The VGA emulation code requires the SMI to be generated
immediately when a VGA access occurs. The SMI genera-
tion hardware can optionally exclude areas of VGA mem-
ory, based on a 32-bit register which has a control bit for
each 2 KB region of the VGA memory window. The control
bit determines whether or not an SMI interrupt is generated
for the corresponding region. The purpose of this hardware
is to allow the VGA emulation software to disable SMI inter-
rupts in VGA memory regions that are not currently dis-
played.
For direct display modes (8-bpp or 16-bpp) in the display
controller, Virtual VGA can operate without SMI generation.
The SMI generation circuit on the GX1 processor has con-
figuration registers to control and mask SMI interrupts in
the VGA memory space.
4.6.2.4 VGA Range Detection
The VGA range detection circuit is similar to the SMI gener-
ation hardware, however, it resides in the internal bus inter-
face address mapping unit. The purpose of this hardware is
to notify the graphics pipeline when accesses to the VGA
memory range A0000h to BFFFFh are detected. The
graphics pipeline has VGA read and write path hardware to
process VGA memory accesses. The VGA range detection
can be configured to trap VGA memory accesses in one or
more of the following ranges: A0000h to AFFFFh
(EGA,VGA), B0000h to B7FFFh (MDA), or B8000h to
BFFFFh (CGA).
4.6.2.5 VGA Sequencer
The VGA sequencer is located at the front end of the
graphics pipeline. The purpose of the VGA sequencer is to
divide up multiple-byte read and write operations into a
sequence of single-byte read and write operations. 16-bit
or 32-bit X-bus write operations to VGA memory are
divided into 8-bit write operations and sent to the VGA write
path. 16-bit or 32-bit X-bus read operations from VGA
memory are accumulated from 8-bit read operations over
the VGA read path. The sequencer generates the lower
two bits of the address.
4.6.2.6 VGA Write/Read Path
The VGA write path implements standard VGA write opera-
tions into VGA memory. No SMI is generated for write path
operations when the VGA access is not displayed. When
the VGA access is displayed, an SMI is generated so that
the SMI emulation can update the frame buffer. The VGA
write path converts 8-bit write operations from the
sequencer into 32-bit VGA memory write operations. The
operations performed by the VGA write path include data
rotation, raster operation (ALU), bit masking, plane select,
plane enable, and write modes.
The VGA read path implements standard VGA read opera-
tions from VGA memory. No SMI is needed for read-path
operations. The VGA read path converts 32-bit read opera-
tions from VGA memory to 8-bit data back to the
sequencer. The basic operations performed by the VGA
read path include color compare, plane-read select, and
read modes.
4.6.2.7 VGA Address Generator
The VGA address generator translates VGA memory
addresses up to the address where the VGA memory
resides on the GX1 processor. The VGA address generator
requires the address from the VGA access (A0000h to
BFFFFh), the base of the VGA memory on the GX1 pro-
cessor, and various control bits. The control bits are neces-
sary because addressing is complicated by odd/even and
Chain 4 addressing modes.
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