GX1 Datasheet, PDF (201/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Electrical Specifications (Continued)
Table 6-16. PCI Interface Signals (Refer to Figures 6-7 and 6-8)
Symbol
Parameter
Min
Max
Unit
t_VAL1
Delay Time, SYSCLK to Signal Valid for Bused Signals
2
11
ns
t_VAL2
Delay Time, SYSCLK to Signal Valid for GNT#^{1, 2}
2
9
ns
t_ON
Delay Time, Float to Active
2
ns
t_OFF
Delay Time, Active to Float
28
ns
t_SU1
Input Setup Time for Bused Signals
7
ns
t_SU2
Input Setup Time for REQ#^{1, 2}
6
ns
t_H
Input Hold Time to SYSCLK
0
ns
1. GNT# and REQ# are point-to-point signals. All other PCI interface signals are bused.
Refer to Chapter 4 of PCI Local Bus Specification, Revision 2.1, for more detailed information.
2. Maximum timings are improved over the PCI Local Bus Specification, Revision 2.1. This allows a PAL or some other
circuit to use a REQ/GNT pair to expand the number of REQ/GNT pairs available to the system.
SYSCLK
OUTPUT
TRI-STATE®
OUTPUT
t_VAL1,2
t_ON
t_OFF
Figure 6-7. Output Timing
SYSCLK
INPUT
t_SU1,2
t_H
Figure 6-8. Input Timing
Revision 1.0
201
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