GX1 Datasheet, PDF (167/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Integrated Functions (Continued)
4.7 PCI CONTROLLER
The GX1 processor includes an integrated PCI controller
with the following features.
4.7.1 X-Bus PCI Slave
• 16-byte PCI write buffer
• 16-byte PCI read buffer from X-bus
• Supports cache line bursting
• Write/Inv line support
• Pacing of data for read or write operations with X-bus
• No active byte enable transfers supported
4.7.2 X-Bus PCI Master
• 16 byte X-bus to PCI write buffer
• Configuration read/write Support
• Int Acknowledge support
• Lock conversion
• Support fast back-to-back cycles as slave
4.7.3 PCI Arbiter
• Fixed, rotating, hybrid, or ping-pong arbitration
(programmable)
• Support four masters, three on PCI
• Internal REQ for CPU
• Master retry mask counter
• Master dead timer
• Resource or total system lock support
4.7.4 Generating Configuration Cycles
Configuration space is a physical address space unique to
PCI. Configuration Mechanism #1 must be used by soft-
ware to generate configuration cycles. Two DWORD I/O
locations are used in this mechanism. The first DWORD
location (CF8h) references a read/write register that is
named CONFIG_ADDRESS. The second DWORD
address (CFCh) references a register named
CONFIG_DATA. The general method for accessing config-
uration space is to write a value into CONFIG_ADDRESS
that specifies a PCI bus, a device on that bus, and a config-
uration register in that device being accessed. A read or
write to CONFIG_DATA will then cause the bridge to trans-
late that CONFIG_ADDRESS value to the requested con-
figuration cycle on the PCI bus.
4.7.5 Generating Special Cycles
A special cycle is a broadcast message to the PCI bus.
Two hardcoded special cycle messages are defined in the
command encode: HALT and SHUTDOWN. Software can
also generate special cycles by using special cycle genera-
tion for configuration mechanism #1 as described in the
PCI Specification 2.1 and briefly described here. To initiate
a special cycle from software, the host must write a value
to CONFIG_ADDRESS encoded as shown in Table 4-40.
The next value written to CONFIG_DATA is the encoded
special cycle. Type 0 or Type 1 conversion will be based on
the Bus Bridge number matching the GX1 processor’s bus
number of 00h.
Table 4-40. Special Cycle Code to CONFIG_ADDRESS¹
31
1
CONFIG
ENABLE
30
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
0000000
RSVD
Bus No. = Bridge
BUS NUMBER
11111
DEVICE NUMBER
111
FUNCTION
NUMBER
1. See Table 4-41 on page 168, bits [1:0] for translation type.
765432 1 0
000000
REGISTER NUMBER TRANS-
LATION
TYPE
Revision 1.0
167
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