GX1 Datasheet, PDF (154/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Integrated Functions (Continued)
4.5.12 Palette Access Registers
These registers are used for accessing the internal palette
RAM and extensions. In addition to the standard 256
entries for 8-bpp color translation, the GX1 processor pal-
ette has extensions for cursor colors and overscan (border)
color.
The Palette Access register group consists of two 32-bit
registers located at GX_BASE+8370h and
GX_BASE+8374h. These registers are summarized in
Table 4-28 on page 141, and Table 4-33 gives their bit for-
mats.
Table 4-33. Display Controller Palette
Bit
Name
Description
GX_BASE+8370h-8373h
DC_PAL_ADDRESS Register (R/W)
Default Value = xxxxxxxxh
31:9
RSVD
8:0
PALETTE_ADDR
GX_BASE+8374h-8377h
Reserved: Set to 0.
Palette Address: The address to be used for the next access to the DC_PAL_DATA register. Each
access to the data register automatically increments the palette address register. If non-sequential
access is made to the palette, the address register must be loaded between each non-sequential
data block. The address ranges are as follows.
Address
0h - FFh
100h
101h
102h
103h
104h
105h - 1FFh
Color
Standard Palette Colors
Cursor Color 0
Cursor Color 1
Reserved
Reserved
Overscan (Color Border)
Not Valid
DC_PAL_DATA Register (R/W)
Default Value = xxxxxxxxh
31:18
RSVD
Reserved: Set to 0.
17:0
PALETTE_DATA _{Palette Data: The read or write data for a palette access.}¹
1. When a read or write to the palette RAM occurs, the previous output value is held for one additional DCLK period. This effect should
go unnoticed and provides for sparkle-free update. Prior to a read or write to this register, the DC_PAL_ADDRESS register should be
loaded with the appropriate address. The address automatically increments after each access to this register, so for sequential access,
the address register need only be loaded once
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