GX1 Datasheet, PDF (219/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Instruction Set (Continued)
8.2.1.2 CPUID Instruction with EAX = 0000 0001h
Standard function 01h (EAX = 1) of the CPUID instruction
returns the processor type, family, model, and stepping
information of the current processor in the EAX register
(see Table 8-18). The EBX and ECX registers are
reserved.
Table 8-18. EAX, EBX, ECX CPUID Data Returned
when EAX = 1
Register
Returned
Contents
Description
EAX[3:0]
EAX[7:4]
EAX[11:8]
EAX[15:12]
EAX[31:16]
EBX
ECX
xx
Stepping ID
4
Model
5
Family
0
Type
-
Reserved
-
Reserved
-
Reserved
Table 8-19. EDX CPUID Data Returned
when EAX = 1 (Continued)
EDX
Returned
Content¹
Feature Flag
CR4
Bit
EDX[12]
EDX[13]
0
Memory Type Range
-
Registers
0
Page Global Enable
-
EDX[14]
0
Machine Check
-
Architecture
EDX[15]
1
Conditional Move
-
Instructions
EDX[16]
0
Page Attribute Table
-
EDX[22:17]
0
Reserved
-
EDX[23]
1
MMX Instructions
-
EDX[24]
0
Fast FPU Save and
-
Restore
EDX[31:25]
0
Reserved
-
1. 0 = Not Supported
The standard feature flags supported are returned in the
EDX register as shown in Table 8-19. Each flag refers to a
specific feature and indicates if that feature is present on
the processor. Some of these features have protection con-
trol in CR4. Before using any of these features on the pro-
cessor, the software should check the corresponding
feature flag. Attempting to execute an unavailable feature
can cause exceptions and unexpected behavior. For exam-
ple, software must check EDX bit 4 before attempting to
use the Time Stamp Counter instruction.
Table 8-19. EDX CPUID Data Returned
when EAX = 1
EDX
Returned
Content¹
Feature Flag
CR4
Bit
EDX[0]
EDX[1]
EDX[2]
EDX[3]
EDX[4]
EDX[5]
EDX[6]
EDX[7]
EDX[8]
EDX[9]
EDX[10]
EDX[11]
1
FPU On-Chip
-
0
Virtual Mode Extension
-
0
Debug Extensions
-
0
Page Size Extensions
-
1
Time Stamp Counter
2
1
RDMSR / WRMSR
-
Instructions
0
Physical Address
-
Extensions
0
Machine Check Excep-
-
tion
1
CMPXCHG8B Instruction
-
0
On-Chip APIC Hardware
-
0
Reserved
-
0
SYSENTER / SYSEXIT
-
Instructions
8.2.1.3 CPUID Instruction with EAX = 00000002h
Standard function 02h (EAX = 02h) of the CPUID instruc-
tion returns information that is specific to the National
Semiconductor family of processors. Information about the
TLB is returned in EAX as shown in Table 8-20. Information
about the L1 cache is returned in EDX.
Table 8-20. Standard CPUID with
EAX = 00000002h
Register
EAX
EAX
EBX
ECX
EDX
Returned
Contents
xx xx 70 xxh
xx xx xx 01h
xx xx xx 80h
Description
TLB is 32 entry, 4-way set asso-
ciative, and has 4 KB pages.
The CPUID instruction needs to
be executed only once with an
input value of 02h to retrieve com-
plete information about the cache
and TLB.
Reserved
Reserved
L1 cache is 16 KB, 4-way set
associated, and has 16 bytes per
line.
Revision 1.0
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