GX1 Datasheet, PDF (120/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Integrated Functions (Continued)
4.3.6 Memory Cycles
Figures 4-5 through 4-8 illustrate various memory cycles
that the memory controller supports. The following subsec-
tions describe some of the supported cycles.
SDRAM Read Cycle
Figure 4-5 shows a SDRAM read cycle. The figure
assumes that a previous ACT command has presented the
row address for the read operation. Note that the burst
length for the READ command is always two.
SDCLK
CS#
RAS#
CAS#
WE#
MA
DQM
MD
COL n
n
n+1
Figure 4-5. Basic Read Cycle with a CAS Latency of Two
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