GX1 Datasheet, PDF (86/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Processor Programming (Continued)
Table 3-35. SMM Memory Space Header Description
Name
Description
DR7
EFLAGS
CR0
Current IP
Next IP
CS Selector
CS Descriptor
N
V
X
M
H
S
P
I
C
I/O Data Size
I/O Address
I/O or Memory Data
Restored ESI or EDI
Memory Address
Debug Register 7: The contents of Debug Register 7.
Extended Flags Register: The contents of Extended Flags Register.
Control Register 0: The contents of Control Register 0.
Current Instruction Pointer: The address of the instruction executed prior to servicing SMM
interrupt.
Next Instruction Pointer: The address of the next instruction that will be executed after exiting
SMM.
Code Segment Selector: Code segment register selector for the current code segment.
Code Segment Descriptor: Encoded descriptor bits for the current code segment.
Nested SMI Status: Flag that determines whether an SMI occurred during SMM (i.e., nested).
SoftVGA SMI Status: SMI was generated by an access to VGA region.
External SMI Status:
If = 1: SMI generated by external SMI# pin.
If = 0: SMI internally generated by Internal Bus Interface Unit.
Memory or I/O Access: 0 = I/O access; 1 = Memory access.
Halt Status: Indicates that the processor was in a halt or shutdown prior to servicing the SMM
interrupt.
Software SMM Entry Indicator:
If = 1: Current SMM is the result of an SMINT instruction.
If = 0: Current SMM is not the result of an SMINT instruction.
REP INSx/OUTSx Indicator:¹
If = 1: Current instruction has a REP prefix.
If = 0: Current instruction does not have a REP prefix.
IN, INSx, OUT, or OUTSx Indicator:¹
If = 1: Current instruction performed is an I/O WRITE.
If = 0: Current instruction performed is an I/O READ.
CS Writable: Code Segment Writable
If = 1: CS is writable.
If = 0: CS is not writable.
Indicates size of data for the trapped I/O cycle:
01h = BYTE
03h = WORD
0Fh = DWORD
Processor port used for the trapped I/O cycle
Data associated with the trapped I/O or memory cycles
Restored ESI or EDI Value: Used when it is necessary to repeat a REP OUTSx or REP INSx
instruction when one of the I/O cycles caused an SMI# trap.¹
Physical address of the operation that caused the SMI
1. INSx = INS, INSB, INSW or INSD instruction.
OUTSx = OUTS, OUTSB, OUTSW and OUTSD instruction.
Size
4 Bytes
4 Bytes
4 Bytes
4 Bytes
4 Bytes
2 Bytes
8 Bytes
1 Bit
1 Bit
1 Bit
1 Bit
1 Bit
1 Bit
1 Bit
1 Bit
1 Bit
2 Bytes
2 Bytes
4 Bytes
4 Bytes
4 Bytes
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