GX1 Datasheet, PDF (103/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Integrated Functions (Continued)
4.2 INTERNAL BUS INTERFACE UNIT
The GX1 processor’s internal bus interface unit provides
control and interface functions to the C-Bus and X-Bus.
The functions on C-Bus include: processor core, FPU,
graphics pipeline, and L1 cache. The functions on X-Bus
include: PCI controller, display controller, memory control-
ler, and graphics accelerator. It provides attribute control for
several sections of memory, and plays an important part in
the Virtual VGA function.
The internal bus interface unit performs functions which
previously required the external pins IGNNE# and A20M#.
The internal bus interface unit provides configuration con-
trol for up to 20 different regions within system memory.
This includes a top-of-memory register and 19 configurable
memory regions in the address space between 640 KB and
1 MB. Each region has separate control for read access,
write access, cacheability, and external PCI master access.
In support of VGA emulation, three of the memory regions
are configurable for use by the graphics pipeline and three
I/O ranges can be programmed to generate SMIs.
4.2.1 FPU Error Support
The FERR# (floating point error) and IGNNE# (ignore
numeric error) pins of the 486 microprocessor have been
replaced with an IRQ13 (interrupt request 13) pin. In DOS
systems, FPU errors are reported by the external vector
13. Emulation of this mode of operation is specified by
clearing the NE bit (bit 5) in the CR0 register. If the NE bit is
active, the IRQ13 output of the GX1 processor is always
driven inactive. If the NE bit is cleared, the GX1 processor
drives IRQ13 active when the ES bit (bit 7) in the FPU Sta-
tus register is set high. Software must respond to this inter-
rupt with an OUT instruction containing an 8-bit operand to
F0h or F1h. When the OUT cycle occurs, the IRQ13 pin is
driven inactive and the FPU starts ignoring numeric errors.
When the ES bit is cleared, the FPU resumes monitoring
numeric errors.
4.2.2 A20M Support
The GX1 processor provides an A20M bit in the
BC_XMAP_1 register (GX_BASE+ 8004h[21]) to replace
the A20M# pin on the 486 microprocessor. When the A20M
bit is set high, all non-SMI accesses will have address bit
20 forced to zero. External hardware must do an SMI trap
on I/O locations that toggle the A20M# pin. The SMI soft-
ware can then change the A20M bit as desired.
This will maintain compatibility with software that depends
on wrapping the address at bit 20.
4.2.3 SMI Generation
The internal bus interface unit can generate SMI interrupts
whenever an I/O cycle is in the VGA address ranges of
3B0h to 3BFh, 3C0h to 3CFh and/or 3D0h to 3DFh. If an
external VGA card is present, the Internal Bus Interface
reset values will not generate an interrupt on VGA
accesses. (Refer to Section 4.6.3 “VGA Configuration Reg-
isters” on page 163 for instructions on how to configure the
registers to enable the SMI interrupt.)
4.2.4 640 KB to 1 MB Region
There are 19 configurable memory regions located
between 640 KB and 1 MB. Three of the regions, A0000h
to AFFFFh, B0000h to B7FFFh, and B8000h to BFFFFh,
are typically used by the graphics subsystem in VGA emu-
lation mode. Each of the these regions has a VGA control
bit that can cause the graphics pipeline to handle accesses
to that section of memory (see Table 4-37 on page 164).
The area between C0000h and FFFFFh is divided into 16
KB segments to form the remaining 16 regions. All 19
regions have four control bits to allow any combination of
read-access, write-access, cache, and external PCI Bus
Master access capabilities (see Table 4-10 on page 106).
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