GX1 Datasheet, PDF (160/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Integrated Functions (Continued)
4.6.1.2 VGA Front End
The VGA front end consists of address and data transla-
tions between the CPU and the frame buffer. This function-
ality is contained within the graphics controller and
sequencer components. Most of the front end functionality
is implemented in the VGA read and write hardware of the
GX1 processor. An important axiom of the VGA is that the
front end and back end are controlled independently. There
are no register fields that control the behavior of both
pieces. Terms like “VGA odd/even mode” are therefore
somewhat misleading; there are two different controls for
odd/even functionality in the front end, and two separate
controls in the refresh path to cause “sensible” refresh
behavior for frame buffer contents written in odd/even
mode. Normally, all these fields would be set up together,
but they don’t have to be. This sort of orthogonal behavior
gives rise to the enormous number of possible VGA
“modes”. The CPU end of the read and write pipelines is
one byte wide. WORD and DWORD accesses from the
CPU to VGA memory are broken down into multiple byte
accesses by the sequencer. For example, a WORD write to
A0000h (in a VGA graphics mode) is processed as if it
were two-byte write operations to A0000h and A0001h.
4.6.1.3 Address Mapping
When a VGA card sees an address on the host bus, bits
[31:15] determine whether the transaction is for the VGA.
Depending on the mode, addresses 000AXXXX,
000B{0xxx}XXX, or 000B{1xxx}XXX can decode into VGA
space. If the access is for the VGA, bits [15:0] provide the
DWORD address into the frame buffer (see odd/even and
Chain 4 modes, next paragraph). Thus, each byte address
on the host bus addresses a DWORD in VGA memory.
On a write transaction, the byte enables are normally
driven from the sequencer’s MapMask register. The VGA
has two other write address mappings that modify this
behavior. In odd/even (Chain 2) write mode, bit 0 of the
address is used to enable bytes 0 and 2 (if zero) or bytes 1
and 3 (if one). In addition, the address presented to the
frame buffer has bit 0 replaced with the PageBit field of the
Miscellaneous Output register. Chain 4 write mode is simi-
lar; only one of the four byte enables is asserted, based on
bits [1:0] of the address, and bits [1:0] of the frame buffer
address are set to zero. In each of these modes, the Map-
Mask enables are logically ANDed into the enables that
result from the address.
4.6.1.4 Video Refresh
VGA refresh is controlled by two units: the CRT controller
(CRTC) and the attribute controller (ATTR). The CRTC pro-
vides refresh addresses and video control; the ATTR pro-
vides the refresh datapath, including pixel formatting and
internal palette lookup.
The VGA back end contains two basic clocks: the dot clock
(or pixel clock) and the character clock. The ClockSelect
field of the Miscellaneous Output register selects a “master
clock” of either 25 MHz or 28 MHz. This master clock,
optionally divided by two, drives the dot clock. The charac-
ter clock is simply the dot clock divided by eight or nine.
The VGA supports four basic pixel formats. Using text for-
mat, the VGA interprets frame buffer values as ASCII char-
acters, foreground/background attributes, and font data.
The other three formats are all “graphics modes”, known as
APA (All Points Addressable) modes. These formats could
be called CGA-compatible (odd/even 4-bpp), EGA-compat-
ible (4-plane 4-bpp), and VGA-compatible (pixel-per-byte 8-
bpp). The format is chosen by the ShiftRegister field of the
Graphics Controller Mode register.
The refresh address pipe is an integral part of the CRTC,
and has many configuration options. Refresh can begin at
any frame buffer address. The display width and the frame
buffer pitch (scan-line delta) are set separately. Multiple
scan lines can be refreshed from the same frame buffer
addresses. The LineCompare register causes the refresh
address to be reset to zero at a particular scan line, provid-
ing support for vertical split-screen.
Within the context of a single scan line, the refresh address
increments by one on every character clock. Before being
presented to the frame buffer, refresh addresses can be
shifted by 0, 1, or 2 bits to the left. These options are often
mis-named BYTE, WORD, and DWORD modes. Using this
shifter, the refresh unit can be programmed to skip one out
of two or three out of four DWORDs of refresh data. As an
example of the utility of this function, consider Chain 4
mode, described in Section 4.6.1.3 “Address Mapping” on
page 160. Pixels written in Chain 4 mode occupy one out of
every four DWORDs in the frame buffer. If the refresh path
is put into “Doubleword” mode, the refresh will come only
from those DWORDs writable in Chain 4. This is how VGA
mode 13h works.
In text mode, the ATTR has a lot of work to do. At each
character clock, it pulls a DWORD of data out of the frame
buffer. In that DWORD, plane 0 contains the ASCII charac-
ter code, and plane 1 contains an attribute byte. The ATTR
uses plane 0 to generate a font lookup address and read
another DWORD. In plane 2, this DWORD contains a bit-
per-pixel representation of one scan line in the appropriate
character glyph. The ATTR transforms these bits into eight
pixels, obtaining foreground and background colors from
the attribute byte. The CRTC must refresh from the same
memory addresses for all scan lines that make up a char-
acter row; within that row, the ATTR must fetch successive
scan lines from the glyph table so as to draw proper char-
acters. Graphics modes are somewhat simpler. In CGA-
compatible mode, a DWORD provides eight pixels. The first
four pixels come from planes 0 and 2; each 4-bit pixel gets
bits [3:2] from plane 2, and bits [1:0] from plane 0. The
remaining four pixels come from planes 1 and 3. The EGA-
compatible mode also gets eight pixels from a DWORD, but
each pixel gets one bit from each plane, with plane 3 pro-
viding bit 3. Finally, VGA-compatible mode gets four pixels
from each DWORD; plane 0 provides the first pixel, plane 1
the next, and so on. The 8-bpp mode uses an option to pro-
vide every pixel for two dot clocks, thus allowing the refresh
pipe to keep up (it only increments on character clocks)
and meaning that the 320-pixel-wide mode 13h really has
640 visible pixels per line. The VGA color model is unusual.
The ATTR contains a 16-entry color palette with 6 bits per
www.national.com
160
Revision 1.0