GX1 Datasheet, PDF (113/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Integrated Functions (Continued)
Bit
Name
GX_BASE+ 8400h-8403h
31:29
28:26
25:23
22
21
20:18
RSVD
RSVD
RSVD
RSVD
RSVD
SDCLKRATE
17
SDCLKSTRT
16:8
RFSHRATE
7:6
RFSHSTAG
5
2CLKADDR
4
RFSHTST
3
XBUSARB
2
SMM_MAP
1
RSVD
0
SDRAMPRG
Table 4-15. Memory Controller Registers
Description
MC_MEM_CNTRL1 (R/W)
Default Value = 248C0040h
Reserved
Reserved
Reserved
Reserved: Set to 0.
Reserved: Must be set to 0. Wait state on the X-Bus x_data during read cycles - for debug only.
SDRAM Clock Ratio: Selects SDRAM clock ratio:
000 = Reserved
001 = ÷ 2
010 = ÷ 2.5
011 = ÷ 3 (Default)
100 = ÷ 3.5
101 = ÷ 4
110 = ÷ 4.5
111 = ÷ 5
Ratio does not take effect until the SDCLKSTRT bit (bit 17 of this register) transitions from 0 to 1.
Start SDCLK: Start operating SDCLK using the new ratio and shift value (selected in bits [20:18] of
this register): 0 = Clear; 1 = Enable.
This bit must transition from zero (written to zero) to one (written to one) in order to start SDCLK or to
change the shift value.
Refresh Interval: This field determines the number of processor core clocks multiplied by 64 between
refresh cycles to the DRAM. By default, the refresh interval is 00h. Refresh is turned off by default.
Refresh Staggering: This field determines number of clocks between the RFSH commands to each of
the four banks during refresh cycles:
00 = 0 SDRAM clocks
01 = 1 SDRAM clocks (Default)
10 = 2 SDRAM clocks
11 = 4 SDRAM clocks
Staggering is used to help reduce power spikes during refresh by refreshing one bank at a time. If only
one bank is installed, this field must be set to 00.
Two Clock Address Setup: Assert memory address for one extra clock before CS# is asserted:
0 = Disable; 1 = Enable.
This can be used to compensate for address setup at high frequencies and/or high loads.
Test Refresh: This bit, when set high, generates a refresh request. This bit is only used for testing pur-
poses.
X-Bus Round Robin: When enabled, processor, graphics pipeline and non-critical display controller
requests are arbitrated at the same priority level. When disabled, processor requests are arbitrated at a
higher priority level. High priority display controller requests always have the highest arbitration priority:
0 = Enable; 1 = Disable.
SMM Region Mapping: Map the SMM memory region at GX_BASE+400000 to physical address
A0000 to BFFFF in SDRAM: 0 = Disable; 1 = Enable.
Reserved: Set to 0.
Program SDRAM: When this bit is set the memory controller will program the SDRAM MRS register
using LTMODE in MC_SYNC_TIM1.
This bit must transition from zero (written to zero) to one (written to one) in order to program the
SDRAM devices.
Revision 1.0
113
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