GX1 Datasheet, PDF (45/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Processor Programming (Continued)
3.3.1.2 Segment Registers
The 16-bit segment registers, part of the main memory
addressing mechanism, are described in Section 3.5 “Off-
set, Segment, and Paging Mechanisms” on page 64. The six
segment registers are:
CS
-
DS
-
SS
-
ES
-
FS
-
GS -
Code Segment
Data Segment
Stack Segment
Extra Segment
Additional Data Segment
Additional Data Segment
The segment registers are used to select segments in main
memory. A segment acts as private memory for different
elements of a program such as code space, data space
and stack space.
There are two segment mechanisms, one for real and vir-
tual 8086 operating modes and one for protected mode.
Initialization and transition to protected mode is described
in Section 3.9.4 “Initialization and Transition to Protected
Mode” on page 93. The segment mechanisms are
described in Section 3.5.2 “Segment Mechanisms” on
page 66.
The active segment register is selected according to the
rules listed in Table 3-3 and the type of instruction being
currently processed. In general, the DS register selector is
used for data references. Stack references use the SS reg-
ister, and instruction fetches use the CS register. While
some selections may be overridden, instruction fetches,
stack operations, and the destination write operation of
string operations cannot be overridden. Special segment-
override instruction prefixes allow the use of alternate seg-
ment registers. These segment registers include the ES,
FS, and GS registers.
3.3.1.3 Instruction Pointer Register
The Instruction Pointer (EIP) register contains the offset
into the current code segment of the next instruction to be
executed. The register is normally incremented by the
length of the current instruction with each instruction exe-
cution unless it is implicitly modified through an interrupt,
exception, or an instruction that changes the sequential
execution flow (for example JMP and CALL).
Table 3-3 illustrates the code segment selection rules.
.
Table 3-3. Segment Register Selection Rules
Type of Memory Reference
Implied (Default)
Segment
Code Fetch
CS
Destination of PUSH, PUSHF, INT, CALL, PUSHA instructions
SS
Source of POP, POPA, POPF, IRET, RET instructions
SS
Destination of STOS, MOVS, REP STOS, REP MOVS instructions
ES
Other data references with effective address using base registers of: DS
EAX, EBX, ECX, EDX, ESI, EDI, EBP, ESP
SS
Segment-Override
Prefix
None
None
None
None
CS, ES, FS, GS, SS
CS, DS, ES, FS, GS
Revision 1.0
45
www.national.com