GX1 Datasheet, PDF (88/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Processor Programming (Continued)
3.7.6 SMM Memory Space
SMM memory space is defined by specifying the base
address and size of the SMM memory space in the SMAR
register. The base address must be a multiple of the SMM
memory space size. For example, a 32 KB SMM memory
space must be located at a 32 KB address boundary. The
memory space size can range from 4 KB to 32 MB. Execution
of the interrupt begins at the base of the SMM memory space.
SMM memory space accesses are always cacheable,
which allows SMM routines to run faster.
3.7.7 SMI Generation for Virtual VGA
The GX1 processor implements SMI generation for VGA
accesses. When enabled memory write operations in
regions A0000h to AFFFFh, B0000h to B7FFFh, and
B8000h to BFFFFh generate an SMI. Memory reads are
not trapped by the GX1 processor. When enabled, the GX1
processor traps I/O addresses for VGA in the following
regions: 3B0h to 3BFh, 3C0h to 3CFh, and 3D0h to 3DFh.
Memory-write trapping is performed during instruction
decode in the processor core. I/O read and write trapping is
implemented in the Internal Bus Interface Unit of the GX1
processor.
The SMI-generation hardware requires two additional con-
figuration registers to control and mask SMI interrupts in
the VGA memory space: VGACTL and VGAM. The
VGACTL register has a control bit for each address range
shown above. The VGAM register has 32 bits that can
selectively disable 2 KB regions within the VGA memory.
The VGAM applies only to the A0000h to AFFFFh region.
If this region is not enabled in VGA_CTL, then the contents
of VGAM is ignored. The purpose of VGAM is to prevent an
SMI from occurring when non-displayed VGA memory is
accessed. This is an enhancement which improves perfor-
mance for double-buffered applications. The format of each
register is shown in Table 4-37 on page 164.
3.7.8 SMM Service Routine Execution
Upon entry into SMM, after the SMM header has been
saved, the CR0, EFLAGS, and DR7 registers are set to
their reset values. The Code Segment (CS) register is
loaded with the base, as defined by the SMAR register, and
a limit of 4 GB. The SMM service routine then begins exe-
cution at the SMM base address in real mode.
The programmer must save, restore the value of any regis-
ters not saved in the header that may be changed by the
SMM service routine. For data accesses immediately after
entering the SMM service routine, the programmer must
use CS as a segment override. I/O port access is possible
during the routine but care must be taken to save registers
modified by the I/O instructions. Before using a segment
register, the register and the register’s descriptor cache con-
tents should be saved using the SVDC instruction.
Hardware interrupts, INTRs and NMIs, may be serviced
during an SMM service routine. If interrupts are to be ser-
viced while executing in the SMM memory space, the SMM
memory space must be within the address range of 0 to 1
MB to guarantee proper return to the SMM service routine
after handling the interrupt.
INTRs are automatically disabled when entering SMM
since the IF flag (EFLAGS register, bit 9) is set to its reset
value. Once in SMM, the INTR can be enabled by setting
the IF flag. An NMI event in SMM can be enabled by setting
NMI_EN high in the CCR3 register (Index C3h[1]). If NMI is
not enabled while in SMM, the CPU latches one NMI event
and services the interrupt after NMI has been enabled or
after exiting SMM through the RSM instruction. Upon
entering SMM, the processor is in real mode, but it may exit
to either real or protected mode depending on its state
when SMM was initiated. The SMM header indicates to
which state it will exit.
Within the SMM service routine, protected mode may be
entered and exited as required, and real or protected mode
device drivers may be called.
To exit the SMM service routine, an RSM instruction, rather
than an IRET, is executed. The RSM instruction causes the
GX1 processor core to restore the CPU state using the
SMM header information and resume execution at the
interrupted point. If the full CPU state was saved by the
programmer, the stored values should be reloaded before
executing the RSM instruction using the MOV, RSDC,
RSLDT and RSTS instructions.
3.7.9 SMI Nesting
The SMI mechanism supports nesting of SMI interrupts
through the SMM service routine the SMI_NEST bit in the
CCR4 register (Index E8h[6]), and the Nested SMI Status
bit (bit N in the SMM header, see Table 3-35 "SMM Mem-
ory Space Header Description" on page 86). Nesting is an
important capability in allowing high-priority events, such
as audio virtualization, to interrupt lower-priority SMI code
for VGA virtualization or power management. SMI_NEST
controls whether SMI interrupts can occur during SMM.
SMM service routines can optionally set SMI_NEST high to
allow higher-priority SMI interrupts while handling the cur-
rent event.
The SMM service routine is responsible for managing the
SMM header data for nested SMI interrupts. The SMM
header must be saved before SMI_NEST is set high, and
SMI_NEST must be cleared and its header information
restored before an RSM instruction is executed.
The Nested SMI Status bit has been added to the SMM
header to show whether the current SMI is nested. The
processor sets Nested SMI Status high if the processor
was in SMM when the SMI was taken. The processor uses
Nested SMI Status on exit to determine whether the pro-
cessor should stay in SMM.
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