PIC18F6X2X Datasheet, PDF (80/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
6.2.4 16-BIT MODE TIMING
The presentation of control signals on the external
memory bus is different for the various operating
modes. Typical signal timing diagrams are shown in
Figure 6-4 through Figure 6-6.
FIGURE 6-4:
EXTERNAL MEMORY BUS TIMING FOR TBLRD (MICROPROCESSOR MODE)
Apparent Q Q1 Q2 Q3 Q4
Actual Q _{Q1 Q2 Q3 Q4}
Q1 Q2
Q1 Q2
Q3 Q4
Q3 Q4
Q4 Q4 Q4 Q4
Q1 Q2 Q3 Q4
A<19:16>
00h
0Ch
AD<15:0>
3AABh
0E55h
CF33h
9256h
BA0
ALE
OE
WRH ‘1’
WRL ‘1’
CE ‘0’
Memory
Cycle
Instruction
Execution
Opcode Fetch
MOVLW 55h
from 007556h
TBLRD Cycle1
‘1’
‘1’
‘0’
1 TCY Wait
Table Read
of 92h
from 199E67h
TBLRD Cycle2
FIGURE 6-5:
EXTERNAL MEMORY BUS TIMING FOR TBLRD
(EXTENDED MICROCONTROLLER MODE)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 _{Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4}
A<19:16>
AD<15:0>
CE
ALE
OE
Memory
Cycle
Instruction
Execution
Opcode Fetch
TBLRD*
from 000100h
INST(PC-2)
0Ch
CF33h
9256h
Opcode Fetch
MOVLW 55h
from 000102h
TBLRD Cycle1
TBLRD 92h
from 199E67h
TBLRD Cycle2
Opcode Fetch
ADDLW 55h
from 000104h
MOVLW
DS39612A-page 78
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