PIC18F6X2X Datasheet, PDF (79/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
6.2.3 16-BIT BYTE SELECT MODE
Figure 6-3 shows an example of 16-bit Byte Select
mode for PIC18F8X2X devices. This mode allows table
write operations to word-wide external memories with
byte selection capability. This generally includes both
word-wide FLASH and SRAM devices.
During a TBLWT cycle, the TABLAT data is presented
on the upper and lower byte of the AD15:AD0 bus. The
WRH signal is strobed for each write cycle; the WRL
pin is not used. The BA0 or UB/LB signals are used to
select the byte to be written based on the Least
Significant bit of the TBLPTR register.
FLASH and SRAM devices use different control signal
combinations to implement Byte Select mode. JEDEC
standard FLASH memories require that a controller I/O
port pin be connected to the memory’s BYTE/WORD
pin to provide the select signal. They also use the BA0
signal from the controller as a byte address. JEDEC
standard static RAM memories, on the other hand, use
the UB or LB signals to select the byte.
FIGURE 6-3:
16-BIT BYTE SELECT MODE EXAMPLE
PIC18F8X2X
AD<7:0>
373
A<20:1>
AD<15:8>
ALE
A<19:16>
OE
WRH
WRL
BA0
I/O
LB
UB
138⁽²⁾
373
A<20:1>
A<x:1>
JEDEC Word
FLASH Memory
D<15:0>
D<15:0>
CE
A0
BYTE/WORD
OE WR⁽¹⁾
A<x:1>
JEDEC Word
SRAM Memory
D<15:0>
CE
D<15:0>
LB
UB OE WR⁽¹⁾
Address Bus
Data Bus
Control Lines
Note 1: This signal only applies to table writes. See Section 5.1, “Table Reads and Writes”.
2: Demultiplexing is only required when multiple memory devices are accessed.
 2003 Microchip Technology Inc.
Advance Information
DS39612A-page 77