PIC18F6X2X Datasheet, PDF (352/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
FIGURE 27-17:
SS
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
SDO
MSb
bit 6 - - - - - -1
LSb
75, 76
77
SDI
MSb In
bit 6 - - - -1
LSb In
74
Note: Refer to Figure 27-4 for load conditions.
TABLE 27-18: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param.
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TssL2scH, SS ↓ to SCK ↓ or SCK ↑ input
TssL2scL
TCY
—
71
TscH
71A
SCK input high time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
72
TscL
72A
SCK input low time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
73A TB2B
Last clock edge of Byte 1 to the first clock edge of Byte 2 1.5 TCY + 40 —
74
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
—
75
TdoR
SDO data output rise time
PIC18F6X2X/8X2X
—
25
PIC18LF6X2X/8X2X
45
76
TdoF
SDO data output fall time
—
25
77
TssH2doZ SS ↑ to SDO output hi-impedance
10
50
78
TscR
SCK output rise time
(Master mode)
PIC18F6X2X/8X2X
—
25
PIC18LF6X2X/8X2X
—
45
79
TscF
SCK output fall time (Master mode)
—
25
80
TscH2doV, SDO data output valid after SCK PIC18F6X2X/8X2X
—
50
TscL2doV edge
PIC18LF6X2X/8X2X
—
100
82
TssL2doV SDO data output valid after SS PIC18F6X2X/8X2X
—
50
↓ edge
PIC18LF6X2X/8X2X
—
100
83
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
1.5 TCY + 40 —
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns (Note 2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS39612A-page 350
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