PIC18F6X2X Datasheet, PDF (56/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on page:
PREINC2
PLUSW2
FSR2H
FSR2L
STATUS
TMR0H
TMR0L
T0CON
OSCCON
LVDCON
WDTCON
RCON
Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented
n/a
(not a physical register)
Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented
n/a
(not a physical register) - value of FSR2 offset by value in WREG
—
—
—
—
Indirect Data Memory Address Pointer 2 High Byte ---- 0000
Indirect Data Memory Address Pointer 2 Low Byte
xxxx xxxx
—
—
—
N
OV
Z
DC
C
---x xxxx
Timer0 Register High Byte
0000 0000
Timer0 Register Low Byte
xxxx xxxx
TMR0ON T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0 1111 1111
—
—
—
—
—
—
—
SCS ---- ---0
—
—
IRVST
LVDEN
LVDL3
LVDL2
LVDL1
LVDL0 --00 0101
—
—
—
—
—
—
—
SWDTE ---- ---0
IPEN
—
—
RI
TO
PD
POR
BOR 0--1 11qq
TMR1H Timer1 Register High Byte
xxxx xxxx
TMR1L
Timer1 Register Low Byte
xxxx xxxx
T1CON
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000
TMR2
Timer2 Register
0000 0000
PR2
Timer2 Period Register
1111 1111
T2CON
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000
SSPBUF
SSPADD
SSP Receive Buffer/Transmit Register
SSP Address Register in I²C Slave mode. SSP Baud Rate Reload Register in I²C Master mode.
xxxx xxxx
0000 0000
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF 0000 0000
SSPCON1 WCOL
SSPOV
SSPEN
CKP
SSPM3 SSPM2 SSPM1 SSPM0 0000 0000
SSPCON2 GCEN ACKSTAT ACKDT ACKEN
RCEN
PEN
RSEN
SEN 0000 0000
ADRESH A/D Result Register High Byte
xxxx xxxx
ADRESL A/D Result Register Low Byte
xxxx xxxx
ADCON0
—
—
CHS3
CHS2
CHS1
CHS0 GO/DONE ADON --00 0000
ADCON1
—
—
VCFG1
VCFG0
PCFG3 PCFG2
PCFG1 PCFG0 --00 0000
ADCON2
ADFM
—
ACQT2
ACQT1
ACQT0 ADCS2
ADCS1 ADCS0 0-00 0000
CCPR1H Enhanced Capture/Compare/PWM Register 1 High Byte
xxxx xxxx
CCPR1L Enhanced Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx
CCP1CON P1M1
P1M0
DC1B1
DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000
CCPR2H Enhanced Capture/Compare/PWM Register 2 High Byte
xxxx xxxx
CCPR2L Enhanced Capture/Compare/PWM Register 2 Low Byte
xxxx xxxx
CCP2CON P2M1
P2M0
DC2B1
DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000
CCPR3H Enhanced Capture/Compare/PWM Register 3 High Byte
xxxx xxxx
CCPR3L Enhanced Capture/Compare/PWM Register 3 Low Byte
xxxx xxxx
CCP3CON P3M1
P3M0
CCP3X
CCP3Y CCP3M3 CCP3M2 CCP3M1 CCP3M0 0000 0000
ECCP1AS ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000
CVRCON CVREN CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0 0000 0000
Legend:
Note 1:
2:
3:
4:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other
Oscillator modes.
Bit 21 of the TBLPTRU allows access to the device configuration bits.
These registers are unused on PIC18F6X2X devices; always maintain these clear.
RG5 is available only if MCLR function is disabled in configuration.
58
58
35, 58
35, 58
35, 60
35, 135
35, 135
35, 133
25, 35
35, 255
35, 269
35, 61,
103
35, 141
35, 141
35, 141
35, 144
35, 144
35, 144
35, 183
35, 183
35, 176
35, 177
35, 187
36, 242
36, 242
36, 235
36, 236
36, 237
36, 174
36, 174
36, 159
36, 174
36, 174
36, 159
36, 174
36, 174
36, 159
36, 171
36, 249
DS39612A-page 54
Advance Information
 2003 Microchip Technology Inc.