PIC18F6X2X Datasheet, PDF (252/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
FIGURE 22-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
VDD VREF+
CVRSS = 0 CVRSS = 1
16 Stages
CVREN
8R
R
R
R
R
CVREF
Note: R is defined in Section 27.0.
16-1 Analog Mux
CVRR
8R
CVRSS = 0
CVRSS = 1
CVR3
VREF-
(From CVRCON<3:0>)
CVR0
22.2 Voltage Reference Accuracy/Error
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(Figure 22-1) keep CVREF from approaching the refer-
ence source rails. The voltage reference is derived
from the reference source; therefore, the CVREF output
changes with fluctuations in that source. The tested
absolute accuracy of the voltage reference can be
found in Section 27.0.
22.3 Operation During SLEEP
When the device wakes up from SLEEP through an
interrupt or a Watchdog Timer time-out, the contents of
the CVRCON register are not affected. To minimize
current consumption in SLEEP mode, the voltage
reference should be disabled.
22.4 Effects of a RESET
A device RESET disables the voltage reference by
clearing bit CVREN (CVRCON<7>). This RESET also
disconnects the reference from the RA2 pin by clearing
bit CVROE (CVRCON<6>) and selects the high volt-
age range by clearing bit CVRR (CVRCON<5>). The
VRSS value select bits, CVRCON<3:0>, are also
cleared.
22.5 Connection Considerations
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be connected to the RF5 pin if the
TRISF<5> bit is set and the CVROE bit is set. Enabling
the voltage reference output onto the RF5 pin with an
input signal present will increase current consumption.
Connecting RF5 as a digital output with VRSS enabled
will also increase current consumption.
The RF5 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, a buffer must be used on the voltage refer-
ence output for external connections to VREF.
Figure 22-2 shows an example buffering technique.
DS39612A-page 250
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