PIC18F6X2X Datasheet, PDF (303/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
LFSR
Load FSR
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
[ label ] LFSR f,k
0≤f≤2
0 ≤ k ≤ 4095
k → FSRf
None
1110
1111
1110 00ff k₁₁kkk
0000 k₇kkk kkkk
The 12-bit literal ‘k’ is loaded into
the file select register pointed to
by ‘f’.
2
Cycles:
2
Q Cycle Activity:
Q1
Q2
Decode
Read literal
‘k’ MSB
Decode
Read literal
‘k’ LSB
Q3
Process
Data
Process
Data
Q4
Write
literal ‘k’
MSB to
FSRfH
Write literal
‘k’ to FSRfL
Example:
LFSR 2, 0x3AB
After Instruction
FSR2H = 0x03
FSR2L = 0xAB
MOVF
Move f
Syntax:
[ label ] MOVF f [,d [,a]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
f → dest
Status Affected: N, Z
Encoding:
0101 00da ffff ffff
Description:
The contents of register ‘f’ are
moved to a destination dependent
upon the status of ‘d’. If ‘d’ is 0, the
result is placed in W. If ‘d’ is 1, the
result is placed back in register ‘f’
(default). Location ‘f’ can be any-
where in the 256-byte bank. If ‘a’ is
0, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register ‘f’
Q3
Process
Data
Q4
Write W
Example:
MOVF REG, 0, 0
Before Instruction
REG = 0x22
W
= 0xFF
After Instruction
REG = 0x22
W
= 0x22
 2003 Microchip Technology Inc.
Advance Information
DS39612A-page 301