PIC18F6X2X Datasheet, PDF (299/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
DECFSZ
Decrement f, skip if 0
Syntax:
[ label ] DECFSZ f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – 1 → dest,
skip if result = 0
Status Affected: None
Encoding:
0010 11da ffff ffff
Description:
The contents of register ‘f’ are dec-
remented. If ‘d’ is 0, the result is
placed in W. If ‘d’ is 1, the result is
placed back in register ‘f’ (default).
If the result is 0, the next instruc-
tion which is already fetched is
discarded and a NOP is executed
instead, making it a two-cycle
instruction. If ‘a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
No
operation
No
operation
Q2
No
operation
No
operation
Q3
No
operation
No
operation
Q4
No
operation
No
operation
Example:
HERE
DECFSZ
GOTO
CONTINUE
CNT, 1, 1
LOOP
Before Instruction
PC
= Address (HERE)
After Instruction
CNT = CNT - 1
If CNT = 0;
PC = Address (CONTINUE)
If CNT ≠ 0;
PC = Address (HERE+2)
DCFSNZ
Decrement f, skip if not 0
Syntax:
[ label ] DCFSNZ f [,d [,a]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – 1 → dest,
skip if result ≠ 0
Status Affected: None
Encoding:
0100 11da ffff ffff
Description:
The contents of register ‘f’ are dec-
remented. If ‘d’ is 0, the result is
placed in W. If ‘d’ is 1, the result is
placed back in register ‘f’ (default).
If the result is 0, the next instruc-
tion which is already fetched is
discarded and a NOP is executed
instead, making it a two-cycle
instruction. If ‘a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
No
operation
No
operation
Q2
No
operation
No
operation
Q3
No
operation
No
operation
Q4
No
operation
No
operation
Example:
HERE
ZERO
NZERO
DCFSNZ TEMP, 1, 0
:
:
Before Instruction
TEMP
=
After Instruction
TEMP
=
If TEMP
=
PC
=
If TEMP
≠
PC
=
?
TEMP - 1,
0;
Address (ZERO)
0;
Address (NZERO)
 2003 Microchip Technology Inc.
Advance Information
DS39612A-page 297