PIC18F6X2X Datasheet, PDF (57/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on page:
CMCON
C2OUT C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0 0000 0000
TMR3H Timer3 Register High Byte
xxxx xxxx
TMR3L
Timer3 Register Low Byte
xxxx xxxx
T3CON
RD16
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000
PSPCON
IBF
OBF
IBOV PSPMODE
—
—
—
—
0000 ----
SPBRG1 USART1 Baud Rate Generator
0000 0000
RCREG1 USART1 Receive Register
0000 0000
TXREG1 USART1 Transmit Register
0000 0000
TXSTA1
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D 0000 -010
RCSTA1
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D 0000 000x
EEADRH
—
—
—
—
—
—
EE Adr Register High ---- --00
EEADR Data EEPROM Address Register
0000 0000
EEDATA Data EEPROM Data Register
0000 0000
EECON2 Data EEPROM Control Register 2 (not a physical register)
---- ----
EECON1
EEPGD
CFGS
—
FREE
WRERR WREN
WR
RD xx-0 x000
IPR3
—
—
RC2IP
TX2IP
TMR4IP CCP5IP CCP4IP CCP3IP --11 1111
PIR3
—
—
RC2IF
TX2IF
TMR4IF CCP5IF CCP4IF CCP3IF --00 0000
PIE3
—
—
RC2IE
TX2IE
TMR4IE CCP5IE CCP4IE CCP3IE --00 0000
IPR2
—
CMIP
—
EEIP
BCLIP
LVDIP TMR3IP CCP2IP -1-1 1111
PIR2
—
CMIF
—
EEIF
BCLIF
LVDIF
TMR3IF CCP2IF -0-0 0000
PIE2
—
CMIE
—
EEIE
BCLIE
LVDIE TMR3IE CCP2IE -0-0 0000
IPR1
PSPIP
ADIP
RCIP
TXIP
SSPIP CCP1IP TMR2IP TMR1IP 1111 1111
PIR1
PSPIF
ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000
PIE1
PSPIE
ADIE
RCIE
TXIE
MEMCON⁽³⁾ EBDIS
—
WAIT1
WAIT0
TRISJ⁽³⁾ Data Direction Control Register for PORTJ
TRISH⁽³⁾ Data Direction Control Register for PORTH
SSPIE
—
CCP1IE
—
TMR2IE
WM1
TMR1IE
WM0
0000 0000
0-00 --00
1111 1111
1111 1111
TRISG
—
—
—
Data Direction Control Register for PORTG
---1 1111
TRISF
Data Direction Control Register for PORTF
1111 1111
TRISE
Data Direction Control Register for PORTE
1111 1111
TRISD
Data Direction Control Register for PORTD
1111 1111
TRISC
Data Direction Control Register for PORTC
1111 1111
TRISB
TRISA
LATJ⁽³⁾
LATH⁽³⁾
Data Direction Control Register for PORTB
—
TRISA6⁽¹⁾ Data Direction Control Register for PORTA
Read PORTJ Data Latch, Write PORTJ Data Latch
Read PORTH Data Latch, Write PORTH Data Latch
1111 1111
-111 1111
xxxx xxxx
xxxx xxxx
LATG
—
—
—
Read PORTG Data Latch, Write PORTG Data Latch
---x xxxx
LATF
Read PORTF Data Latch, Write PORTF Data Latch
xxxx xxxx
LATE
Read PORTE Data Latch, Write PORTE Data Latch
xxxx xxxx
LATD
Read PORTD Data Latch, Write PORTD Data Latch
xxxx xxxx
LATC
Read PORTC Data Latch, Write PORTC Data Latch
xxxx xxxx
LATB
LATA
Read PORTB Data Latch, Write PORTB Data Latch
—
LATA6⁽¹⁾ Read PORTA Data Latch, Write PORTA Data Latch⁽¹⁾
xxxx xxxx
-xxx xxxx
Legend:
Note 1:
2:
3:
4:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other
Oscillator modes.
Bit 21 of the TBLPTRU allows access to the device configuration bits.
These registers are unused on PIC18F6X2X devices; always maintain these clear.
RG5 is available only if MCLR function is disabled in configuration.
36, 243
36, 147
36, 147
36, 147
36, 131
36, 219
36, 226
36, 224
36, 216
36, 217
36, 85
36, 85
36, 85
36, 85
36, 82
37, 102
37, 96
37, 99
37, 101
37, 95
37, 98
37, 100
37, 94
37, 97
37, 73
37, 129
37, 126
37, 121
37, 118
37, 115
37, 112
37, 110
37, 107
37, 123
37, 129
37, 126
37, 123
37, 121
37, 118
37, 115
37, 112
37, 110
37, 107
 2003 Microchip Technology Inc.
Advance Information
DS39612A-page 55