PIC18F6X2X Datasheet, PDF (275/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
24.4 Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 FLASH devices differs significantly from other
PICmicro^® devices.
The user program memory is divided on binary bound-
aries into four blocks of 16 Kbytes each. The first block is
further divided into a boot block of 2048 bytes and a
second block (Block 0) of 14 Kbytes.
Each of the blocks has three code protection bits
associated with them. They are:
• Code Protect bit (CPn)
• Write Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 24-3 shows the program memory organization
for 48 and 64-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 24-3.
FIGURE 24-3:
CODE PROTECTED PROGRAM MEMORY FOR PIC18F6X2X/8X2X DEVICES
MEMORY SIZE/DEVICE
48 Kbytes
(PIC18FX525
64 Kbytes
(PIC18FX621)
Boot Block
Boot Block
Block 0
Block 0
Block 1
Block 1
Block 2
Block 2
Unimplemented Read ‘0’
Block 3
Address
Range
000000h
0007FFh
000800h
003FFFh
004000h
007FFFh
008000h
00BFFFh
00C000h
00FFFFh
Block Code Protection
Controlled By:
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
TABLE 24-3: SUMMARY OF CODE PROTECTION REGISTERS
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
300008h CONFIG5L
—
—
—
300009h CONFIG5H CPD
CPB
—
30000Ah CONFIG6L
—
—
—
30000Bh CONFIG6H WRTD WRTB WRTC
30000Ch CONFIG7L
—
—
—
30000Dh CONFIG7H —
EBTRB
—
Legend: Shaded cells are unimplemented.
* Unimplemented in PIC18FX585 devices.
—
CP3*
—
—
—
WRT3*
—
—
—
EBTR3*
—
—
Bit 2
CP2
—
WRT2
—
EBTR2
—
Bit 1
CP1
—
WRT1
—
EBTR1
—
Bit 0
CP0
—
WRT0
—
EBTR0
—
 2003 Microchip Technology Inc.
Advance Information
DS39612A-page 273