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PIC18F6X2X Datasheet, PDF (276/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D | |||
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PIC18F6X2X/8X2X
24.4.1 PROGRAM MEMORY
CODE PROTECTION
The user memory may be read to or written from any
location using the table read and table write instruc-
tions. The device ID may be read with table reads. The
Configuration registers may be read and written with
the table read and table write instructions.
In user mode, the CPn bits have no direct effect. CPn
bits inhibit external reads and writes. A block of user
memory may be protected from table writes if the
WRTn configuration bit is â0â. The EBTRn bits control
table reads. For a block of user memory with the
EBTRn bit set to â0â, a table read instruction that exe-
cutes from within that block is allowed to read. A table
read instruction that executes from a location outside of
that block is not allowed to read and will result in read-
ing â0âs. Figures 24-4 through 24-6 illustrate table write
and table read protection.
Note:
Code protection bits may only be written to
a â0â from a â1â state. It is not possible to
write a â1â to a bit in the â0â state. Code pro-
tection bits are only set to â1â by a full chip
erase or block erase function. The full chip
erase and block erase functions can only
be initiated via ICSP or an external
programmer.
FIGURE 24-4:
TABLE WRITE (WRTn) DISALLOWED
Register Values
TBLPTR = 000FFFh
Program Memory
000000h
0007FFh
000800h
PC = 003FFEh
TBLWT*
003FFFh
004000h
PC = 008FFEh
TBLWT*
007FFFh
008000h
00BFFFh
00C000h
00FFFFh
Configuration Bit Settings
WRTB,EBTRB = 11
WRT0,EBTR0 = 01
WRT1,EBTR1 = 11
WRT2,EBTR2 = 11
WRT3,EBTR3 = 11
Results: All table writes disabled to Block n whenever WRTn = 0.
DS39612A-page 274
Advance Information
 2003 Microchip Technology Inc.
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