PIC18F6X2X Datasheet, PDF (12/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
FIGURE 1-2:
PIC18F8525/8621 BLOCK DIAGRAM
Data Bus<8>
21 ^{Table Pointer<21>}
8
8
21
inc/dec logic
Data Latch
Data RAM
(3.8 Kbytes)
Address Latch
Program Memory
(48/64 Kbytes)
Data Latch
20
PCLATU PCLATH
Address Latch
12
PCU PCH PCL
Program Counter
31 Level Stack
Address<12>
4
BSR
12
FSR0
FSR1
FSR2
4
Bank0, F
12
Table Latch
Decode
inc/dec
logic
16
8
ROM Latch
IR
AD15:AD0, A19:16⁽⁴⁾
Instruction
Decode &
Control
OSC2/CLKO
OSC1/CLKI
Timing
Generation
Precision
Bandgap
Reference
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Test Mode
Select
8
PRODH PRODL
3
BITOP
8
8 x 8 Multiply
8
W
8
8
8
ALU<8>
8
PORTA
PORTB
PORTC
PORTD
PORTE
PORTF
PORTG
VDD, VSS
MCLR⁽³⁾
BOR
Data
LVD ^{EEPROM Timer0}
Timer1
Timer2
Timer3
Timer4
10-bit
ADC
PORTH
Comparator ECCP1 ECCP2 ECCP3 CCP4 CCP5 MSSP EUSART1 EUSART2
PORTJ
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/LVDIN
OSC2/CLKO/RA6
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3/CCP2⁽¹⁾/P2A⁽¹⁾
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2⁽¹⁾/P2A⁽¹⁾
RC2/CCP1/P1A
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX1/CK1
RC7/RX1/DT1
RD7/PSP7:RD0/PSP0⁽⁴⁾
RE0/RD/P2D⁽⁴⁾
RE1/WR/P2C⁽⁴⁾
RE2/CS/P2B⁽⁴⁾
RE3/P3C^(2,4)
RE4/P3B^(2,4)
RE5/P1C^(2,4)
RE6/P1B^(2,4)
RE7/CCP2⁽¹⁾/P2A^(1,4)
RF0/AN5
RF1/AN6/C2OUT
RF2/AN7/C1OUT
RF3/AN8
RF4/AN9
RF5/AN10/CVREF
RF6/AN11
RF7/SS
RG0/CCP3/P3A
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4/P3D
RG4/CCP5/P1D
RG5⁽³⁾
RH0:RH3/AD19⁽⁴⁾
RH4/AN12/P3C⁽²⁾
RH5/AN13/P3B⁽²⁾
RH6/AN14/P1C⁽²⁾
RH7/AN15/P1B⁽²⁾
RJ0/ALE
RJ1/OE
RJ2/WRL
RJ3/WRH
RJ4/BA0
RJ5/CE
RJ6/LB
RJ7/UB
Note 1: CCP2/P2A are multiplexed with RC1 when CCP2MX is set; with RE7 when CCP2MX is cleared and the device is configured in
Microcontroller mode; or with RB3 when CCP2MX is cleared in all other Program Memory modes.
2: P1B/P1C/P3B/P3C are multiplexed with RE6:RE3 when ECCPMX is set, and with RH7:RH4 when ECCPMX is not set.
3: RG5 is multiplexed with MCLR, and is only available when the MCLR Resets are disabled.
4: External memory interface pins are multiplexed with PORTD (AD7:AD0), PORTE (AD15:AD8) and PORTH (A19:A16).
DS39612A-page 10
Advance Information
 2003 Microchip Technology Inc.