PIC18F6X2X Datasheet, PDF (274/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
FIGURE 24-2:
WAKE-UP FROM SLEEP THROUGH INTERRUPT^(1,2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
OSC1
CLKO⁽⁴⁾
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
TOST⁽²⁾
INT pin
INTF Flag
(INTCON<1>)
Interrupt Latency⁽³⁾
GIEH bit
(INTCON<7>)
INSTRUCTION FLOW
PC
PC
Instruction
Fetched
Inst(PC) = SLEEP
Instruction
Executed
Inst(PC - 1)
PC + 2
Inst(PC + 2)
SLEEP
Processor in
SLEEP
PC + 4
PC + 4
Inst(PC + 4)
Inst(PC + 2)
PC + 4
Dummy Cycle
0008h
Inst(0008h)
Dummy Cycle
000Ah
Inst(000Ah)
Inst(0008h)
Note 1: XT, HS or LP Oscillator mode assumed.
2: GIE = 1 assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.
3: TOST = 1024 TOSC (drawing not to scale). This delay will not occur for RC and EC Osc modes.
4: CLKO is not available in these Osc modes but shown here for timing reference.
DS39612A-page 272
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