PIC18F6X2X Datasheet, PDF (310/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
RETFIE
Return from Interrupt
Syntax:
[ label ] RETFIE [s]
Operands:
s ∈ [0,1]
Operation:
(TOS) → PC,
1 → GIE/GIEH or PEIE/GIEL,
if s = 1
(WS) → W,
(STATUSS) → STATUS,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged.
Status Affected: GIE/GIEH, PEIE/GIEL.
Encoding:
0000 0000 0001 000s
Description:
Return from Interrupt. Stack is
popped and Top-of-Stack (TOS) is
loaded into the PC. Interrupts are
enabled by setting either the high
or low priority global interrupt
enable bit. If ‘s’ = 1, the contents of
the shadow registers WS,
STATUSS and BSRS are loaded
into their corresponding registers,
W, STATUS and BSR. If ‘s’ = 0, no
update of these registers occurs
(default).
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Q2
Decode
No
operation
No
operation
No
operation
Q3
No
operation
No
operation
Q4
Pop PC from
stack
Set GIEH or
GIEL
No
operation
Example:
RETFIE 1
After Interrupt
PC
=
W
=
BSR
=
STATUS
=
GIE/GIEH, PEIE/GIEL =
TOS
WS
BSRS
STATUSS
1
RETLW
Return Literal to W
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
[ label ] RETLW k
0 ≤ k ≤ 255
k → W,
(TOS) → PC,
PCLATU, PCLATH are unchanged
None
0000 1100 kkkk kkkk
W is loaded with the eight-bit literal
‘k’. The program counter is loaded
from the top of the stack (the return
address). The high address latch
(PCLATH) remains unchanged.
1
2
Q Cycle Activity:
Q1
Decode
Q2
Read
literal ‘k’
No
operation
No
operation
Q3
Process
Data
No
operation
Q4
Pop PC from
stack, Write
to W
No
operation
Example:
CALL TABLE ; W contains table
; offset value
; W now has
; table value
:
TABLE
ADDWF PCL ; W = offset
RETLW k0 ; Begin table
RETLW k1 ;
:
:
RETLW kn ; End of table
Before Instruction
W
= 0x07
After Instruction
W
= value of kn
DS39612A-page 308
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 2003 Microchip Technology Inc.