PIC18F6X2X Datasheet, PDF (128/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
TABLE 10-15: PORTH FUNCTIONS
Name
Bit#
Buffer Type
Function
RH0/A16
bit 0
ST/TTL⁽¹⁾ Input/output port pin or address bit 16 for external memory interface.
RH1/A17
bit 1
ST/TTL⁽¹⁾ Input/output port pin or address bit 17 for external memory interface.
RH2/A18
bit 2
ST/TTL⁽¹⁾ Input/output port pin or address bit 18 for external memory interface.
RH3/A19
bit 3
ST/TTL⁽¹⁾ Input/output port pin or address bit 19 for external memory interface.
RH4/AN12/P3C⁽²⁾ bit 4
ST
Input/output port pin, analog input channel 12 or Enhanced PWM
output P3C.
RH5/AN13/P3B⁽²⁾ bit 5
ST
Input/output port pin, analog input channel 13 or Enhanced PWM
output P3B.
RH6/AN14/P1C⁽²⁾ bit 6
ST
Input/output port pin, analog input channel 14 or Enhanced PWM
output P1C.
RH7/AN15/P1B⁽²⁾ bit 7
ST
Input/output port pin, analog input channel 15 or Enhanced PWM3
output P1B.
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus or Parallel Slave
Port mode.
2: Valid only for PIC18F8X2X devices when ECCPMX is not set. The alternate assignments for
P1B/P1C/P3B/P3C in all PIC18F6X2X devices and in PIC18F8X2X devices when ECCPMX is set are RE6,
RE5, RE4 and RE3, respectively.
TABLE 10-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
TRISH
PORTH Data Direction Control Register
1111 1111
PORTH Read PORTH pin/Write PORTH Data Latch
xxxx xxxx
LATH
Read PORTH Data Latch/Write PORTH Data Latch
xxxx xxxx
ADCON1
—
— VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000
MEMCON EBDIS — WAIT1 WAIT0 —
—
WM1 WM0 0-00 --00
Legend: x = unknown, u = unchanged, - = unimplemented. Shaded cells are not used by PORTH.
Value on
all other
RESETS
1111 1111
uuuu uuuu
uuuu uuuu
--00 0000
0-00 --00
DS39612A-page 126
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