PIC18F6X2X Datasheet, PDF (141/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

12.2 Timer1 Oscillator
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscilla-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. The circuit for a typical LP oscilla-
tor is shown in Figure 12-3. Table 12-1 shows the
capacitor selection for the Timer1 oscillator.
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator
FIGURE 12-3:
C1
33 pF
EXTERNAL
COMPONENTS FOR THE
TIMER1 LP OSCILLATOR
PIC18F6X2X/8X2X
T1OSI
XTAL
32.768 kHz
C2
33 pF
T1OSO
Note:
See the notes with Table 12-1 for additional
information about capacitor selection.
TABLE 12-1: CAPACITOR SELECTION
FOR THE ALTERNATE
OSCILLATOR
Osc Type
Freq
C1
C2
LP
32 kHz
TBD⁽¹⁾
TBD⁽¹⁾
Crystal to be Tested:
32.768 kHz Epson C-001R32.768K-A ± 20 PPM
Note 1: Microchip suggests 33 pF as a starting
point in validating the oscillator circuit.
2: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
4: Capacitor values are for design guidance
only.
PIC18F6X2X/8X2X
12.3 Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit, TMR1IF
(PIR1<0>). This interrupt can be enabled/disabled by
setting/clearing TMR1 interrupt enable bit, TMR1IE
(PIE1<0>).
12.4 Resetting Timer1 Using an ECCP
Special Trigger Output
If either the ECCP1 or ECCP2 module is configured in
Compare mode to generate a “special event trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1. The trigger for ECCP2 will also start an A/D
conversion if the A/D module is enabled.
Note:
The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Timer1 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this RESET operation may not work.
In the event that a write to Timer1 coincides with a
special event trigger from ECCP1, the write will take
precedence.
In this mode of operation, the CCPR1H:CCPR1L regis-
ter pair effectively becomes the period register for
Timer1.
12.5 Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see Figure 12-2). When the RD16 control bit
(T1CON<7>) is set, the address for TMR1H is mapped
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 high byte buffer. This provides
the user with the ability to accurately read all 16 bits of
Timer1 without having to determine whether a read of
the high byte, followed by a read of the low byte, is valid
due to a rollover between reads.
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. Timer1 high byte is
updated with the contents of TMR1H when a write
occurs to TMR1L. This allows a user to write all 16 bits
to both the high and low bytes of Timer1 at once.
The high byte of Timer1 is not directly readable or writ-
able in this mode. All reads and writes must take place
through the Timer1 High Byte Buffer register. Writes to
TMR1H do not clear the Timer1 prescaler. The
prescaler is only cleared on writes to TMR1L.
 2003 Microchip Technology Inc.
Advance Information
DS39612A-page 139