PIC18F6X2X Datasheet, PDF (33/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
3.0 RESET
The PIC18F6X2X/8X2X devices differentiate between
various kinds of RESET:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during SLEEP
d) Watchdog Timer (WDT) Reset (during normal
operation)
e) Programmable Brown-out Reset (BOR)
f) RESET Instruction
g) Stack Full Reset
h) Stack Underflow Reset
Most registers are unaffected by a RESET. Their status
is unknown on POR and unchanged by all other
RESETS. The other registers are forced to a “RESET
state” on Power-on Reset, MCLR, WDT Reset, Brown-
out Reset, MCLR Reset during SLEEP and by the
RESET instruction.
Most registers are not affected by a WDT wake-up
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCON register, RI, TO, PD,
POR and BOR, are set or cleared differently in different
RESET situations as indicated in Table 3-2. These bits
are used in software to determine the nature of the
RESET. See Table 3-3 for a full description of the
RESET states of all registers.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 3-1.
The enhanced MCU devices have a MCLR noise filter
in the MCLR Reset path. The filter will detect and
ignore small pulses. The MCLR pin is not driven low by
any internal RESETS, including the WDT.
FIGURE 3-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET Instruction
Stack ^{Stack Full/Underflow Reset}
Pointer
MCLR
VDD
OSC1
External Reset
WDT
Module
WDT
Time-out
Reset
SLEEP
VDD Rise Power-on Reset
Detect
Brown-out
Reset
BOREN
OST/PWRT
OST
10-bit Ripple Counter
S
Chip_Reset
R
Q
PWRT
On-chip
RC OSC⁽¹⁾
10-bit Ripple Counter
Enable PWRT
Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.
2: See Table 3-1 for time-out situations.
Enable OST⁽²⁾
 2003 Microchip Technology Inc.
Advance Information
DS39612A-page 31