PIC18F6X2X Datasheet, PDF (156/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
16.3 Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCP4
pin can be:
• driven high
• driven low
• toggled (high to low or low to high)
• remain unchanged (that is, reflects the state of the
I/O latch)
The action on the pin is based on the value of the mode
select bits (CCP4M3:CCP4M0). At the same time, the
interrupt flag bit CCP4IF is set.
16.3.1 CCP PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
Note:
Clearing the CCP4CON register will force
the RG3/CCP4 compare output latch to
the default low level. This is not the
PORTG I/O data latch.
16.3.2 TIMER1/TIMER3 MODE SELECTION
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
16.3.3 SOFTWARE INTERRUPT MODE
When the Generate Software Interrupt mode is chosen
(CCP4M3:CCP4M0 = 1010), the CCP4 pin is not
affected. Only a CCP interrupt is generated if enabled
and the CCP4IE bit is set.
16.3.4 SPECIAL EVENT TRIGGER
Although shown in Figure 16-3, the compare on match
special event triggers are not implemented on CCP4 or
CCP5; they are only available on ECCP1 and ECCP2.
Their operation is discussed in detail in Section 17.2.1.
FIGURE 16-3:
COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger
(ECCP1 and ECCP2 only)
Set Flag bit CCP4IF
RG3/CCP4 pin
TRISG<3>
Output Enable
QS
R
Output
Logic
CCP4CON<3:0>
Mode Select
Match
CCPR4H CCPR4L
Comparator
T3CCP2
01
TMR1H TMR1L
TMR3H TMR3L
DS39612A-page 154
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