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PIC18F6X2X Datasheet, PDF (316/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D | |||
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PIC18F6X2X/8X2X
SUBWFB
Subtract W from f with Borrow
Syntax:
[ label ] SUBWFB f [,d [,a]
Operands:
0 ⤠f ⤠255
d â [0,1]
a â [0,1]
Operation:
(f) â (W) â (C) â dest
Status Affected: N, OV, C, DC, Z
Encoding:
0101 10da ffff ffff
Description:
Subtract W and the carry flag (bor-
row) from register âfâ (2âs complement
method). If âdâ is 0, the result is stored
in W. If âdâ is 1, the result is stored
back in register âfâ (default). If âaâ is 0,
the Access Bank will be selected,
overriding the BSR value. If âaâ is 1,
then the bank will be selected as per
the BSR value (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register âfâ
Q3
Process
Data
Q4
Write to
destination
Example 1:
SUBWFB REG, 1, 0
Before Instruction
REG
W
C
= 0x19
= 0x0D
=1
After Instruction
REG
W
C
Z
N
= 0x0C
= 0x0D
=1
=0
=0
(0001 1001)
(0000 1101)
(0000 1011)
(0000 1101)
; result is positive
Example 2:
SUBWFB REG, 0, 0
Before Instruction
REG
W
C
= 0x1B
= 0x1A
=0
After Instruction
REG
W
C
Z
N
= 0x1B
= 0x00
=1
=1
=0
(0001 1011)
(0001 1010)
(0001 1011)
; result is zero
Example 3:
SUBWFB REG, 1, 0
Before Instruction
REG
W
C
= 0x03
= 0x0E
=1
After Instruction
REG = 0xF5
W
= 0x0E
C
=0
Z
=0
N
=1
(0000 0011)
(0000 1101)
(1111 0100)
; [2âs comp]
(0000 1101)
; result is negative
SWAPF
Swap f
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
[ label ] SWAPF f [,d [,a]
0 ⤠f ⤠255
d â [0,1]
a â [0,1]
(f<3:0>) â dest<7:4>,
(f<7:4>) â dest<3:0>
None
0011 10da ffff ffff
The upper and lower nibbles of reg-
ister âfâ are exchanged. If âdâ is 0,
the result is placed in W. If âdâ is 1,
the result is placed in register âfâ
(default). If âaâ is 0, the Access
Bank will be selected, overriding
the BSR value. If âaâ is 1, then the
bank will be selected as per the
BSR value (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register âfâ
Q3
Process
Data
Q4
Write to
destination
Example:
SWAPF REG, 1, 0
Before Instruction
REG = 0x53
After Instruction
REG = 0x35
DS39612A-page 314
Advance Information
 2003 Microchip Technology Inc.
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