PIC18F6X2X Datasheet, PDF (225/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
19.2 USART Asynchronous Mode
The Asynchronous mode of operation is selected by
clearing the SYNC bit (TXSTAx<4>). In this mode, the
USART uses standard non-return-to-zero (NRZ) format
(one START bit, eight or nine data bits and one STOP
bit). The most common data format is 8 bits. An on-chip
dedicated 8-bit/16-bit baud rate generator can be used
to derive standard baud rate frequencies from the
oscillator.
The USART transmits and receives the LSb first. The
USART’s transmitter and receiver are functionally inde-
pendent but use the same data format and baud rate.
The baud rate generator produces a clock, either x16
or x64 of the bit shift rate depending on the BRGH and
BRG16 bits (TXSTAx<2> and BAUDCONx<3>). Parity
is not supported by the hardware but can be
implemented in software and stored as the 9th data bit.
When operating in Asynchronous mode, the USART
module consists of the following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
• Auto Wake-up on Sync Break Character
• 12-bit Break Character Transmit
• Auto Baud Rate Detection
19.2.1 USART ASYNCHRONOUS
TRANSMITTER
The USART transmitter block diagram is shown in
Figure 19-2. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREGx. The TXREGx register is loaded with data in
software. The TSR register is not loaded until the STOP
bit has been transmitted from the previous load. As
soon as the STOP bit is transmitted, the TSR is loaded
with new data from the TXREGx register (if available).
Once the TXREGx register transfers the data to the TSR
register (occurs in one TCY), the TXREGx register is
empty and flag bit TXIF (PIR1<4>) is set. This interrupt
can be enabled/disabled by setting/clearing enable bit
TXIE (PIE1<4>). Flag bit TXIF will be set regardless of
the state of enable bit TXIE and cannot be cleared in
software. Flag bit TXIF is not cleared immediately upon
loading the Transmit Buffer register, TXREGx. TXIF
becomes valid in the second instruction cycle following
the load instruction. Polling TXIF immediately following a
load of TXREGx will return invalid results.
While flag bit TXIF indicates the status of the TXREGx
register, another bit, TRMT (TXSTAx<1>), shows the
status of the TSR register. Status bit TRMT is a read
only bit which is set when the TSR register is empty. No
interrupt logic is tied to this bit so the user has to poll
this bit in order to determine if the TSR register is
empty.
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
is set.
To set up an Asynchronous Transmission:
1. Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
5. Enable the transmission by setting bit TXEN
which will also set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREGx register (starts
transmission).
If using interrupts, ensure that the GIE and PEIE bits in
the INTCON register (INTCON<7:6>) are set.
FIGURE 19-2:
USART TRANSMIT BLOCK DIAGRAM
TXIE
TXIF
MSb
(8)
Interrupt
TXEN Baud Rate CLK
BRG16
SPBRGHx SPBRGx
Baud Rate Generator
Data Bus
TXREGx Register
8
LSb
•••
0
TSR Register
Pin Buffer
and Control
TX9
TX9D
TRMT
SPEN
TX pin
 2003 Microchip Technology Inc.
Advance Information
DS39612A-page 223