PIC18F6X2X Datasheet, PDF (124/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
10.7 PORTG, TRISG and LATG
Registers
PORTG is a 6-bit wide port with 5 bi-directional pins
(RG0:RG4) and one optional input only pin (RG5). The
corresponding Data Direction register is TRISG. Setting
a TRISG bit (= 1) will make the corresponding PORTG
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISG bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATG) is also memory
mapped. Read-modify-write operations on the LATG
register, read and write the latched output value for
PORTG.
PORTG is multiplexed with both CCP and USART
functions (Table 10-13). PORTG pins have Schmitt
Trigger input buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the corre-
sponding peripheral section for the correct TRIS bit
settings.
Note: On a Power-on Reset, these pins are
configured as digital inputs.
The pin override value is not loaded into the TRIS reg-
ister. This allows read-modify-write operations of the
TRIS register without concern due to peripheral
overrides.
The sixth pin of PORTG (MCLR/VPP/RG5) is a digital
input pin. Its operation is controlled by the MCLRE
configuration bit in Configuration Register 3H
(CONFIG3H<7>). In its default configuration
(MCLRE = 1), the pin functions as the device Master
Clear input. When selected as a port pin (MCLRE = 0),
it functions as an input only pin; as such, it does not
have TRISG or LATG bits associated with it.
In either configuration, RG5 also functions as the
programming voltage input during device programming.
Note 1: On a Power-on Reset, RG5 is enabled as
a digital input only if Master Clear
functionality is disabled (MCLRE = 0).
2: If the device Master Clear is disabled,
verify that either of the following is done to
ensure proper entry into ICSP mode:
a.) disable low voltage programming
(CONFIG4L<2> = 0); or
b.) make certain that RB5/KBI1/PGM is
held low during entry into ICSP.
EXAMPLE 10-7: INITIALIZING PORTG
CLRF
CLRF
MOVLW
MOVWF
PORTG
LATG
0x04
TRISG
; Initialize PORTG by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RG1:RG0 as outputs
; RG2 as input
; RG4:RG3 as inputs
FIGURE 10-16: PORTG BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
PORTG/Peripheral Out Select
Peripheral Data Out
RD LATG
Data Bus
WR LATG or
WR PORTG
WR TRISG
DQ
CK Q
Data Latch
DQ
CK Q
TRIS Latch
0
1
TRIS
Override
Logic
TRIS OVERRIDE
Pin Override
Peripheral
VDD
RG0
Yes
CCP3 I/O
P
RG1
Yes
USART1 Async Xmit,
Sync Clock
RG2
Yes
USART1 Async Rcv,
I/O pin⁽¹⁾
RG3
Yes
Sync Data Out
CCP4 I/O
N
RG4
Yes
CCP5 I/O
Note 1: I/O pins have diode protection to VDD
VSS
and VSS.
2: Peripheral output enable is only active
if peripheral select is active.
RD TRISG
Peripheral Output
Enable⁽²⁾
RD PORTG
Peripheral Data In
Schmitt
Trigger
Q
D
EN
DS39612A-page 122
Advance Information
 2003 Microchip Technology Inc.