PIC18F6X2X Datasheet, PDF (343/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
FIGURE 27-7:
PROGRAM MEMORY READ TIMING DIAGRAM
OSC1
A<19:16>
BA0
AD<15:0>
ALE
CE
Q1
Q2
Q3
Q4
Q1
Address
150
151
164
171
Address
160
155
167
166
168
Data from External
163
162
161
169
171A
OE
165
Operating Conditions: 2.0V < VCC < 5.5V, -40°C < TA < 125°C unless otherwise stated.
Q2
Address
Address
TABLE 27-9: CLKO AND I/O TIMING REQUIREMENTS
Param.
No
Symbol
Characteristics
Min
Typ
Max
Units
150 TadV2alL Address out valid to ALE ↓ (address
setup time)
0.25 TCY – 10
—
—
ns
151 TalL2adl ALE ↓ to address out invalid (address hold
5
time)
—
—
ns
155 TalL2oeL ALE ↓ to OE ↓
10
0.125 TCY
—
ns
160 TadZ2oeL AD high-Z to OE ↓ (bus release to OE)
0
—
—
ns
161 ToeH2adD OE ↑ to AD driven
0.125 TCY – 5
—
—
ns
162 TadV2oeH LS Data valid before OE ↑ (data setup time)
20
—
—
ns
163 ToeH2adl OE ↑ to data in invalid (data hold time)
0
—
—
ns
164 TalH2alL ALE pulse width
—
TCY
—
ns
165 ToeL2oeH OE pulse width
0.5 TCY – 5 0.5 TCY
—
ns
166 TalH2alH ALE ↑ to ALE ↑ (cycle time)
—
0.25 TCY
—
ns
167 Tacc
Address valid to data valid
0.75 TCY – 25
—
—
ns
168 Toe
OE ↓ to data valid
—
0.5 TCY – 25 ns
169 TalL2oeH ALE ↓ to OE ↑
0.625 TCY – 10 — 0.625 TCY + 10 ns
171 TalH2csL Chip Enable active to ALE ↓
0.25 TCY – 20
—
—
ns
171A TubL2oeH AD valid to Chip Enable active
—
—
10
ns
 2003 Microchip Technology Inc.
Advance Information
DS39612A-page 341