PIC18F6X2X Datasheet, PDF (153/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
16.0 CAPTURE/COMPARE/PWM
(CCP) MODULES
PIC18F6X2X/8X2X devices all have a total of five CCP
(Capture/Compare/PWM) modules. Two of these
(CCP4 and CCP5) implement standard Capture, Com-
pare and Pulse Width Modulation (PWM) modes, and
are discussed in this section. The other three modules
(ECCP1, ECCP2, ECCP3) implement standard Cap-
ture and Compare modes, as well as enhanced PWM
modes. These are discussed in Section 17.0.
Each CCP/ECCP module contains a 16-bit register
which can operate as a 16-bit Capture register, a 16-bit
Compare register or a PWM Master/Slave Duty Cycle
register. For the sake of clarity, all CCP module opera-
tion in the following sections is described with respect
to CCP4, but is equally applicable to CCP5.
Capture and Compare operations described in this
chapter apply to all standard and enhanced CCP mod-
ules. The operations of PWM mode described in
Section 16.4 applies to CCP4 and CCP5 only.
Note:
Throughout this section and Section 17.0,
references to register and bit names that
may be associated with a specific CCP
module are referred to generically by the
use of ‘x’ or ‘y’ in place of the specific mod-
ule number. Thus, “CCPxCON” might refer
to the control register for CCP4 or CCP5, or
ECCP1, ECCP2 or ECCP3. “CCPxCON” is
used throughout these sections to refer to
the module control register, regardless of
whether the CCP module is a standard or
enhanced implementation.
REGISTER 16-1:
CCPxCON REGISTER (CCP4 AND CCP5 MODULES)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
DCxB1 DCxB0 CCPxM3 CCPxM2
bit 7
R/W-0 R/W-0
CCPxM1 CCPxM0
bit 0
bit 7-6
bit 5-4
bit 3-0
Unimplemented: Read as ‘0’
DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 for CCP Module x
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbits
(DCx9:DCx2) of the duty cycle are found in CCPRxL.
CCPxM3:CCPxM0: CCP Module x Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode; initialize CCP pin low; on compare match, force CCP pin high
(CCPIF bit is set)
1001 = Compare mode; initialize CCP pin high; on compare match, force CCP pin low
(CCPIF bit is set)
1010 = Compare mode; generate software interrupt on compare match (CCPIF bit is set,
CCP pin reflects I/O state)
1011 = Reserved
11xx = PWM mode
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
 2003 Microchip Technology Inc.
Advance Information
DS39612A-page 151