PIC18F6X2X Datasheet, PDF (104/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
REGISTER 9-12:
IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
U-0
U-0
R/W-1 R/W-1 R/W-1 R/W-1
—
—
RC2IP TX2IP TMR4IP CCP5IP
bit 7
R/W-1
CCP4IP
R/W-1
CCP3IP
bit 0
bit 7-6
bit 5
bit 4
bit 3
bit 2-0
Unimplemented: Read as ‘0’
RC2IP: USART2 Receive Interrupt Priority bit
1 = High priority
0 = Low priority
TX2IP: USART2 Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
TMR4IP: TMR4 to PR4 Match Interrupt Priority bit
1 = High priority
0 = Low priority
CCPxIP: CCPx Interrupt Priority bit (ECCP3, CCP4 and CCP5)
1 = High priority
0 = Low priority
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS39612A-page 102
Advance Information
 2003 Microchip Technology Inc.