PIC18F6X2X Datasheet, PDF (378/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
RETFIE ............................................................................ 308
RETLW ............................................................................. 308
RETURN .......................................................................... 309
Revision History ............................................................... 365
RLCF ................................................................................ 309
RLNCF ............................................................................. 310
RRCF ............................................................................... 310
RRNCF ............................................................................. 311
S
SCK .................................................................................. 175
SDI ................................................................................... 175
SDO ................................................................................. 175
Serial Clock, SCK ............................................................. 175
Serial Data In (SDI) .......................................................... 175
Serial Data Out (SDO) ..................................................... 175
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 311
Slave Select (SS) ............................................................. 175
Slave Select Synchronization ........................................... 181
SLEEP .............................................................. 259, 271, 312
Software Simulator (MPLAB SIM) .................................... 320
Software Simulator (MPLAB SIM30) ................................ 320
Special Event Trigger. See Compare (ECCP Mode).
Special Event Trigger. See Compare (ECCP Module).
Special Features of the CPU ............................................ 259
Configuration Registers .................................... 261–267
Special Function Registers ................................................ 49
Map ............................................................................ 51
SPI Mode
Associated Registers ............................................... 183
Bus Mode Compatibility ........................................... 183
Effects of a RESET .................................................. 183
Master Mode ............................................................ 180
Master/Slave Connection ......................................... 179
Serial Clock .............................................................. 175
Serial Data In ........................................................... 175
Serial Data Out ......................................................... 175
Slave Mode .............................................................. 181
Slave Select ............................................................. 175
Slave Select Synchronization ................................... 181
SLEEP Operation ..................................................... 183
SPI Clock ................................................................. 180
SS .................................................................................... 175
SSP
TMR2 Output for Clock Shift ............................ 143, 144
TMR4 Output for Clock Shift .................................... 150
SSPOV Status Flag .......................................................... 205
SSPSTAT Register
R/W Bit ............................................................. 188, 189
STATUS Bits
Significance and Initialization Condition for
RCON Register .................................................. 33
SUBFWB .......................................................................... 312
SUBLW ............................................................................ 313
SUBWF ............................................................................ 313
SUBWFB .......................................................................... 314
SWAPF ............................................................................ 314
T
Table Pointer Operations (Table) ....................................... 66
TBLRD ............................................................................. 315
TBLWT ............................................................................. 316
Time-out in Various Situations ........................................... 33
Timer0 .............................................................................. 133
16-bit Mode Timer Reads and Writes ...................... 135
Associated Registers ............................................... 135
Clock Source Edge Select (T0SE Bit) ..................... 135
Clock Source Select (T0CS Bit) ............................... 135
Operation ................................................................. 135
Overflow Interrupt .................................................... 135
Prescaler. See Prescaler, Timer0.
Timer1 .............................................................................. 137
16-bit Read/Write Mode ........................................... 139
Associated Registers ............................................... 141
Operation ................................................................. 138
Oscillator ...........................................................137, 139
Overflow Interrupt .............................................137, 139
Special Event Trigger (ECCP) ..........................139, 162
TMR1H Register ...................................................... 137
TMR1L Register ....................................................... 137
Use as a Real-Time Clock ....................................... 140
Timer2 .............................................................................. 143
Associated Registers ............................................... 144
Operation ................................................................. 143
Postscaler. See Postscaler, Timer2.
PR2 Register ............................................143, 156, 162
Prescaler. See Prescaler, Timer2.
SSP Clock Shift ................................................143, 144
TMR2 Register ......................................................... 143
TMR2 to PR2 Match Interrupt ........... 143, 144, 156, 162
Timer3 .............................................................................. 145
Associated Registers ............................................... 147
Operation ................................................................. 146
Oscillator ...........................................................145, 147
Overflow Interrupt .............................................145, 147
Special Event Trigger (ECCP) ................................. 147
TMR3H Register ...................................................... 145
TMR3L Register ....................................................... 145
Timer4 .............................................................................. 149
Associated Registers ............................................... 150
Operation ................................................................. 149
Postscaler. See Postscaler, Timer4.
PR4 Register ........................................................... 149
Prescaler. See Prescaler, Timer4.
SSP Clock Shift ....................................................... 150
TMR4 Register ......................................................... 149
TMR4 to PR4 Match Interrupt ...........................149, 150
Timing Diagrams
A/D Conversion ........................................................ 357
Acknowledge Sequence .......................................... 208
Asynchronous Reception ......................................... 226
Asynchronous Transmission .................................... 224
Asynchronous Transmission (Back to Back) ........... 224
Auto Wake-up Bit (WUE) During
Normal Operation ............................................ 227
Auto Wake-up Bit (WUE) During SLEEP ................. 227
Automatic Baud Rate Calculation ............................ 222
Baud Rate Generator with Clock Arbitration ............ 202
BRG Reset Due to SDA Arbitration During
START Condition ............................................. 211
Brown-out Reset (BOR) ........................................... 343
Bus Collision During a Repeated
START Condition (Case 1) .............................. 212
Bus Collision During a Repeated
START Condition (Case 2) .............................. 212
Bus Collision During a START Condition
(SCL = 0) ......................................................... 211
DS39612A-page 376
Advance Information
 2003 Microchip Technology Inc.