PIC18F6X2X Datasheet, PDF (43/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

4.0 MEMORY ORGANIZATION
There are three memory blocks in PIC18F6X2X/8X2X
devices. They are:
• Program Memory
• Data RAM
• Data EEPROM
Data and program memory use separate busses which
allows for concurrent access of these blocks. Additional
detailed information for FLASH program memory and
data EEPROM is provided in Section 5.0 and
Section 7.0, respectively.
In addition to on-chip FLASH, the PIC18F8X2X devices
are also capable of accessing external program mem-
ory through an external memory bus. Depending on the
selected operating mode (discussed in Section 4.1.1),
the controllers may access either internal or external
program memory exclusively, or both internal and
external memory in selected blocks. Additional infor-
mation on the external memory interface is provided in
Section 6.0.
4.1 Program Memory Organization
A 21-bit program counter is capable of addressing the
2-Mbyte program memory space. Accessing a location
between the physically implemented memory and the
2-Mbyte address will cause a read of all ‘0’s (a NOP
instruction).
The PIC18F6525 and PIC18F8525 each have
48 Kbytes of on-chip FLASH memory, while the
PIC18F6621 and PIC18F8621 have 64 Kbytes of
FLASH. This means that PIC18FX525 devices can
store internally up to 24,576 single word instructions,
and PIC18FX621 devices can store up to 32,768 single
word instructions.
The RESET vector address is at 0000h, and the
interrupt vector addresses are at 0008h and 0018h.
Figure 4-1 shows the program memory map for
PIC18FX525 devices, while Figure 4-2 shows the
program memory map for PIC18FX621 devices.
PIC18F6X2X/8X2X
4.1.1
PIC18F6X2X/8X2X PROGRAM
MEMORY MODES
PIC18F8X2X devices differ significantly from their
PIC18 predecessors in their utilization of program
memory. In addition to available on-chip FLASH pro-
gram memory, these controllers can also address up to
2 Mbytes of external program memory through the
external memory interface. There are four distinct
operating modes available to the controllers:
• Microprocessor (MP)
• Microprocessor with Boot Block (MPBB)
• Extended Microcontroller (EMC)
• Microcontroller (MC)
The Program Memory mode is determined by setting
the two Least Significant bits of the CONFIG3L
Configuration Byte register as shown in Register 4-1.
(See also Section 24.1 for additional details on the
device configuration bits.)
The Program Memory modes operate as follows:
• The Microprocessor Mode permits access only
to external program memory; the contents of the
on-chip FLASH memory are ignored. The 21-bit
program counter permits access to a 2-MByte
linear program memory space.
• The Microprocessor with Boot Block Mode
accesses on-chip FLASH memory from addresses
000000h to 0007FFh. Above this, external program
memory is accessed all the way up to the 2-MByte
limit. Program execution automatically switches
between the two memories as required.
• The Microcontroller Mode accesses only
on-chip FLASH memory. Attempts to read above
the physical limit of the on-chip FLASH (BFFFh for
the PIC18FX525, FFFFh for the PIC18FX621)
causes a read of all ‘0’s (a NOP instruction).
The Microcontroller mode is also the only operating
mode available to PIC18F6X2X devices.
• The Extended Microcontroller Mode allows
access to both internal and external program
memories as a single block. The device can
access its entire on-chip FLASH memory; above
this, the device accesses external program mem-
ory up to the 2-MByte program space limit. As
with Boot Block mode, execution automatically
switches between the two memories as required.
In all modes, the microcontroller has complete access
to data RAM and EEPROM.
Figure 4-3 compares the memory maps of the different
Program Memory modes. The differences between
on-chip and external memory access limitations are
more fully explained in Table 4-1.
 2003 Microchip Technology Inc.
Advance Information
DS39612A-page 41