PIC18F6X2X Datasheet, PDF (235/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
19.4.2 USART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical except in the case of SLEEP or any
IDLE mode and bit SREN, which is a “don't care” in
Slave mode.
If receive is enabled by setting the CREN bit prior to
entering SLEEP or any IDLE mode, then a word may
be received while in this Low Power mode. Once the
word is received, the RSR register will transfer the data
to the RCREGx register; if the RCIE enable bit is set,
the interrupt generated will wake the chip from Low
Power mode. If the global interrupt is enabled, the
program will branch to the interrupt vector.
To set up a Synchronous Slave Reception:
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. If interrupts are desired, set enable bit RCIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
5. Flag bit RCIF will be set when reception is com-
plete. An interrupt will be generated if enable bit
RCIE was set.
6. Read the RCSTAx register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREGx register.
8. If any error occurred, clear the error by clearing
bit CREN.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 19-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
RESETS
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000
PIR1
—
ADIF
RCIF TXIF
— CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1
—
ADIE
RCIE TXIE
— CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1
—
ADIP
RCIP TXIP
— CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
RCSTAx
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
RCREGx USART Receive Register
0000 0000 0000 0000
TXSTAx
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
BAUDCONx
—
RCIDL
—
SCKP BRG16 —
WUE ABDEN -1-0 0-00 -1-0 0-00
SPBRGHx Baud Rate Generator Register, High Byte
0000 0000 0000 0000
SPBRGx Baud Rate Generator Register, Low Byte
0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
 2003 Microchip Technology Inc.
Advance Information
DS39612A-page 233