PIC18F6X2X Datasheet, PDF (148/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
14.1 Timer3 Operation
Timer3 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>).
When TMR3CS = 0, Timer3 increments every instruc-
tion cycle. When TMR3CS = 1, Timer3 increments on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T13CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored and the pins are read as ‘0’.
Timer3 also has an internal “RESET input”. This RESET
can be generated by the CCP module (Section 14.0).
FIGURE 14-1:
TIMER3 BLOCK DIAGRAM
TMR3IF
Overflow
Interrupt
Flag bit
TMR3H
CLR
TMR3L
CCP Special Trigger
T3CCPx
0
TMR3ON
On/Off
1
T3SYNC
Synchronized
Clock Input
T1OSO/
T13CKI
T1OSI
T1OSC
(3)
1
T1OSCEN _FOSC/4
Enable
Oscillator⁽¹⁾
Internal
Clock
0
TMR3CS
Prescaler
1, 2, 4, 8
2
T3CKPS1:T3CKPS0
Synchronize
det
SLEEP Input
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 14-2:
TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE
Data Bus<7:0>
8
TMR3H
Write TMR3L
8
8
Read TMR3L
Set TMR3IF Flag bit
on Overflow
8
TMR3
Timer3
High Byte
CLR
TMR3L
T1OSO/
T13CKI
T1OSI
To Timer1 Clock Input
T1OSC
T1OSCEN
Enable
Oscillator⁽¹⁾
CCP Special Trigger
T3CCPx
0
Synchronized
Clock Input
TMR3ON
On/Off
1
T3SYNC
FOSC/4
Internal
Clock
1
Prescaler
1, 2, 4, 8
0
2
T3CKPS1:T3CKPS0
TMR3CS
Synchronize
det
SLEEP Input
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS39612A-page 146
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 2003 Microchip Technology Inc.