PIC18F6X2X Datasheet, PDF (11/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
FIGURE 1-1:
PIC18F6525/6621 BLOCK DIAGRAM
Data Bus<8>
21
Address Latch
Program Memory
(48/64 Kbytes)
Data Latch
21 ^{Table Pointer<21>}
8
8
inc/dec logic
20
PCLATU PCLATH
PCU PCH PCL
Program Counter
31 Level Stack
Data Latch
Data RAM
( 3.8 Kbytes )
Address Latch
12
Address<12>
4
BSR
12
FSR0
FSR1
FSR2
4
Bank 0, F
12
Table Latch
16
8
ROM Latch
inc/dec
Decode _logic
IR
Instruction
Decode &
Control
OSC2/CLKO
OSC1/CLKI
Timing
Generation
Precision
Bandgap
Reference
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Test Mode
Select
8
PRODH PRODL
3
BITOP
8
8 x 8 Multiply
8
W
8
8
8
ALU<8>
8
VDD, VSS
MCLR⁽²⁾
BOR
LVD
Data
EEPROM ^Timer0
Timer1
Timer2
Timer3
Timer4
10-bit
ADC
PORTA
PORTB
PORTC
PORTD
PORTE
PORTF
PORTG
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/LVDIN
OSC2/CLKO/RA6
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2⁽¹⁾/P2A⁽¹⁾
RC2/CCP1/P1A
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX1/CK1
RC7/RX1/DT1
RD7/PSP7 :RD0/PSP0
RE0/RD/P2D
RE1/WR/P2C
RE2/CS/P2B
RE3/P3C
RE4/P3B
RE5/P1C
RE6/P1B
RE7/CCP2⁽¹⁾/P2A⁽¹⁾
RF0/AN5
RF1/AN6/C2OUT
RF2/AN7/C1OUT
RF3/AN8
RF4/AN9
RF5/AN10/CVREF
RF6/AN11
RF7/SS
RG0/CCP3/P3A
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4/P3D
RG4/CCP5/P1D
RG5⁽²⁾
Comparator ECCP1 ECCP2 ECCP3 CCP4 CCP5 MSSP EUSART1 EUSART2
Note 1: CCP2/P2A are multiplexed with RC1 when CCP2MX is set, or RE7 when CCP2MX is not set.
2: RG5 is multiplexed with MCLR, and is only available when the MCLR Resets are disabled.
 2003 Microchip Technology Inc.
Advance Information
DS39612A-page 9