PIC18F6X2X Datasheet, PDF (293/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
BTG
Bit Toggle f
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
[ label ] BTG f,b[,a]
0 ≤ f ≤ 255
0≤b<7
a ∈ [0,1]
(f<b>) → f<b>
None
0111 bbba ffff ffff
Bit ‘b’ in data memory location ‘f’ is
inverted. If ‘a’ is 0, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register ‘f’
Q3
Process
Data
Q4
Write
register ‘f’
Example:
BTG
PORTC, 4, 0
Before Instruction:
PORTC = 0111 0101 [0x75]
After Instruction:
PORTC = 0110 0101 [0x65]
BOV
Branch if Overflow
Syntax:
[ label ] BOV n
Operands:
-128 ≤ n ≤ 127
Operation:
if overflow bit is ’1’
(PC) + 2 + 2n → PC
Status Affected: None
Encoding:
1110 0100 nnnn nnnn
Description:
If the Overflow bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
No
operation
If No Jump:
Read literal
‘n’
No
operation
Process
Data
No
operation
Write to PC
No
operation
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
If Overflow =
PC
=
If Overflow =
PC
=
BOV Jump
address (HERE)
1;
address (Jump)
0;
address (HERE+2)
 2003 Microchip Technology Inc.
Advance Information
DS39612A-page 291