PIC18F6X2X Datasheet, PDF (288/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
BCF
Bit Clear f
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
[ label ] BCF
0 ≤ f ≤ 255
0≤b≤7
a ∈ [0,1]
0 → f<b>
None
f,b[,a]
1001 bbba ffff ffff
Bit ‘b’ in register ‘f’ is cleared. If ‘a’
is 0, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register ‘f’
Q3
Process
Data
Q4
Write
register ‘f’
Example:
BCF
Before Instruction
FLAG_REG =
After Instruction
FLAG_REG =
FLAG_REG, 7, 0
0xC7
0x47
BN
Branch if Negative
Syntax:
[ label ] BN n
Operands:
-128 ≤ n ≤ 127
Operation:
if negative bit is ’1’
(PC) + 2 + 2n → PC
Status Affected: None
Encoding:
1110 0110 nnnn nnnn
Description:
If the Negative bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
No
operation
If No Jump:
Read literal
‘n’
No
operation
Process
Data
No
operation
Write to PC
No
operation
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
If Negative =
PC
=
If Negative =
PC
=
BN Jump
address (HERE)
1;
address (Jump)
0;
address (HERE+2)
DS39612A-page 286
Advance Information
 2003 Microchip Technology Inc.