PIC18F6X2X Datasheet, PDF (132/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
10.10 Parallel Slave Port
PORTD also operates as an 8-bit wide parallel slave
port, or microprocessor port, when control bit
PSPMODE (PSPCON<4>) is set. It is asynchronously
readable and writable by the external world through RD
control input pin, RE0/RD and WR control input pin,
RE1/WR.
Note:
For PIC18F8X2X devices, the parallel
slave port is available only in
Microcontroller mode.
The PSP can directly interface to an 8-bit micro-
processor data bus. The external microprocessor can
read or write the PORTD latch as an 8-bit latch. Setting
bit PSPMODE enables port pin RE0/RD to be the RD
input, RE1/WR to be the WR input and RE2/CS to be
the CS (chip select) input. For this functionality, the cor-
responding data direction bits of the TRISE register
(TRISE<2:0>) must be configured as inputs (set). The
A/D port configuration bits PCFG2:PCFG0
(ADCON1<2:0>) must be set, which will configure pins
RE2:RE0 as digital I/O.
A write to the PSP occurs when both the CS and WR
lines are first detected low. A read from the PSP occurs
when both the CS and RD lines are first detected low.
The PORTE I/O pins become control inputs for the
microprocessor port when bit PSPMODE
(PSPCON<4>) is set. In this mode, the user must make
sure that the TRISE<2:0> bits are set (pins are config-
ured as digital inputs) and the ADCON1 is configured
for digital I/O. In this mode, the input buffers are TTL.
FIGURE 10-24:
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
Data Bus
DQ
WR LATD
or
PORTD
CK
Data Latch
Q
D
RD PORTD
ENEN
TRIS Latch
RDx
Pin
TTL
RD LATD
One bit of PORTD
Set Interrupt Flag
PSPIF (PIR1<7>)
Read
TTL
RD
Chip Select
TTL
CS
Write
TTL
WR
Note: I/O pin has protection diodes to VDD and VSS.
DS39612A-page 130
Advance Information
 2003 Microchip Technology Inc.