PIC18F6X2X Datasheet, PDF (37/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
FSR1H
FSR1L
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
---- 0000
xxxx xxxx
---- 0000
uuuu uuuu
---- uuuu
uuuu uuuu
BSR
PIC18F6X2X PIC18F8X2X
---- 0000
---- 0000
---- uuuu
INDF2
PIC18F6X2X PIC18F8X2X
N/A
N/A
N/A
POSTINC2 PIC18F6X2X PIC18F8X2X
N/A
N/A
N/A
POSTDEC2 PIC18F6X2X PIC18F8X2X
N/A
N/A
N/A
PREINC2
PIC18F6X2X PIC18F8X2X
N/A
N/A
N/A
PLUSW2
PIC18F6X2X PIC18F8X2X
N/A
N/A
N/A
FSR2H
FSR2L
STATUS
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
---- 0000
xxxx xxxx
---x xxxx
---- 0000
uuuu uuuu
---u uuuu
---- uuuu
uuuu uuuu
---u uuuu
TMR0H
PIC18F6X2X PIC18F8X2X
0000 0000
uuuu uuuu
uuuu uuuu
TMR0L
PIC18F6X2X PIC18F8X2X
xxxx xxxx
uuuu uuuu
uuuu uuuu
T0CON
PIC18F6X2X PIC18F8X2X
1111 1111
1111 1111
uuuu uuuu
OSCCON
PIC18F6X2X PIC18F8X2X
---- 0000
---- 0000
---- uuuu
LVDCON
WDTCON
RCON⁽⁴⁾
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
--00 0101
---- ---0
0--1 11qq
--00 0101
---- ---0
0--1 qquu
--uu uuuu
---- ---u
u--1 qquu
TMR1H
PIC18F6X2X PIC18F8X2X
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1L
PIC18F6X2X PIC18F8X2X
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
PIC18F6X2X PIC18F8X2X
0-00 0000
u-uu uuuu
u-uu uuuu
TMR2
PIC18F6X2X PIC18F8X2X
0000 0000
0000 0000
uuuu uuuu
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
1111 1111
-000 0000
xxxx xxxx
0000 0000
0000 0000
1111 1111
-000 0000
uuuu uuuu
0000 0000
0000 0000
1111 1111
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
SSPCON1 PIC18F6X2X PIC18F8X2X
0000 0000
0000 0000
uuuu uuuu
SSPCON2 PIC18F6X2X PIC18F8X2X
0000 0000
0000 0000
uuuu uuuu
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
See Table 3-2 for RESET value for specific condition.
Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
Oscillator modes, they are disabled and read ‘0’.
Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
If MCLR function is disabled, PORTG<5> is a read only bit.
 2003 Microchip Technology Inc.
Advance Information
DS39612A-page 35