PIC18F6X2X Datasheet, PDF (36/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
TOSU
TOSH
TOSL
STKPTR
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
uu-0 0000
---0 uuuu⁽³⁾
uuuu uuuu⁽³⁾
uuuu uuuu⁽³⁾
uu-u uuuu⁽³⁾
PCLATU
PIC18F6X2X PIC18F8X2X
--00 0000
--00 0000
--uu uuuu
PCLATH
PCL
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PC + 2⁽²⁾
TBLPTRU
PIC18F6X2X PIC18F8X2X
--00 0000
--00 0000
--uu uuuu
TBLPTRH
PIC18F6X2X PIC18F8X2X
0000 0000
0000 0000
uuuu uuuu
TBLPTRL
PIC18F6X2X PIC18F8X2X
0000 0000
0000 0000
uuuu uuuu
TABLAT
PIC18F6X2X PIC18F8X2X
0000 0000
0000 0000
uuuu uuuu
PRODH
PIC18F6X2X PIC18F8X2X
xxxx xxxx
uuuu uuuu
uuuu uuuu
PRODL
INTCON
INTCON2
INTCON3
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
xxxx xxxx
0000 000x
1111 1111
1100 0000
uuuu uuuu
0000 000x
1111 1111
1100 0000
uuuu uuuu
uuuu uuuu⁽¹⁾
uuuu uuuu⁽¹⁾
uuuu uuuu⁽¹⁾
INDF0
PIC18F6X2X PIC18F8X2X
N/A
N/A
N/A
POSTINC0 PIC18F6X2X PIC18F8X2X
N/A
N/A
N/A
POSTDEC0 PIC18F6X2X PIC18F8X2X
N/A
N/A
N/A
PREINC0
PIC18F6X2X PIC18F8X2X
N/A
N/A
N/A
PLUSW0
PIC18F6X2X PIC18F8X2X
N/A
N/A
N/A
FSR0H
PIC18F6X2X PIC18F8X2X
---- 0000
---- 0000
---- uuuu
FSR0L
PIC18F6X2X PIC18F8X2X
xxxx xxxx
uuuu uuuu
uuuu uuuu
WREG
PIC18F6X2X PIC18F8X2X
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF1
PIC18F6X2X PIC18F8X2X
N/A
N/A
N/A
POSTINC1 PIC18F6X2X PIC18F8X2X
N/A
N/A
N/A
POSTDEC1 PIC18F6X2X PIC18F8X2X
N/A
N/A
N/A
PREINC1
PIC18F6X2X PIC18F8X2X
N/A
N/A
N/A
PLUSW1
PIC18F6X2X PIC18F8X2X
N/A
N/A
N/A
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
See Table 3-2 for RESET value for specific condition.
Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
Oscillator modes, they are disabled and read ‘0’.
Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
If MCLR function is disabled, PORTG<5> is a read only bit.
DS39612A-page 34
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 2003 Microchip Technology Inc.