PIC18F6X2X Datasheet, PDF (312/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
RLNCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Rotate Left f (no carry)
[ label ] RLNCF f [,d [,a]
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f<n>) → dest<n+1>,
(f<7>) → dest<0>
N, Z
0100 01da ffff ffff
The contents of register ‘f’ are
rotated one bit to the left. If ‘d’ is 0,
the result is placed in W. If ‘d’ is 1,
the result is stored back in register
‘f’ (default). If ‘a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ is 1, then the
bank will be selected as per the
BSR value (default).
register f
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register ‘f’
Q3
Process
Data
Q4
Write to
destination
Example:
RLNCF
REG, 1, 0
Before Instruction
REG = 1010 1011
After Instruction
REG = 0101 0111
RRCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Rotate Right f through Carry
[ label ] RRCF f [,d [,a]
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f<n>) → dest<n-1>,
(f<0>) → C,
(C) → dest<7>
C, N, Z
0011 00da ffff ffff
The contents of register ‘f’ are
rotated one bit to the right through
the Carry flag. If ‘d’ is 0, the result is
placed in W. If ‘d’ is 1, the result is
placed back in register ‘f’ (default).
If ‘a’ is 0, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ is 1, then the bank will be
selected as per the BSR value
(default).
C
register f
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register ‘f’
Q3
Process
Data
Q4
Write to
destination
Example:
RRCF
REG, 0, 0
Before Instruction
REG = 1110 0110
C
=0
After Instruction
REG =
W
=
C
=
1110 0110
0111 0011
0
DS39612A-page 310
Advance Information
 2003 Microchip Technology Inc.