PIC18F6X2X Datasheet, PDF (291/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
BRA
Unconditional Branch
Syntax:
[ label ] BRA n
Operands:
-1024 ≤ n ≤ 1023
Operation:
(PC) + 2 + 2n → PC
Status Affected: None
Encoding:
1101 0nnn nnnn nnnn
Description:
Add the 2’s complement number
‘2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is a
two-cycle instruction.
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
Read literal
‘n’
No
operation
Process
Data
No
operation
Write to PC
No
operation
Example:
HERE
BRA Jump
Before Instruction
PC
= address (HERE)
After Instruction
PC
= address (Jump)
BSF
Bit Set f
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
[ label ] BSF
0 ≤ f ≤ 255
0≤b≤7
a ∈ [0,1]
1 → f<b>
None
f,b[,a]
1000 bbba ffff ffff
Bit ‘b’ in register ‘f’ is set. If ‘a’ is 0,
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value.
1
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register ‘f’
Q3
Process
Data
Q4
Write
register ‘f’
Example:
BSF
Before Instruction
FLAG_REG =
After Instruction
FLAG_REG =
FLAG_REG, 7, 1
0x0A
0x8A
 2003 Microchip Technology Inc.
Advance Information
DS39612A-page 289