PIC18F6X2X Datasheet, PDF (31/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

2.8 Power-up Delays
Power-up delays are controlled by two timers so that no
external RESET circuitry is required for most applica-
tions. The delays ensure that the device is kept in
RESET until the device power supply and clock are sta-
ble. For additional information on RESET operation,
see Section 3.0, “Reset”.
The first timer is the Power-up Timer (PWRT) which
optionally provides a fixed delay of 72 ms (nominal) on
power-up only (POR and BOR). The second timer is
the Oscillator Start-up Timer (OST), intended to keep
the chip in RESET until the crystal oscillator is stable.
PIC18F6X2X/8X2X
With the PLL enabled (HS+PLL and EC+PLL Oscillator
mode), the time-out sequence following a Power-on
Reset is different from other Oscillator modes. The
time-out sequence is as follows: First, the PWRT time-
out is invoked after a POR time delay has expired.
Then, the Oscillator Start-up Timer (OST) is invoked.
However, this is still not a sufficient amount of time to
allow the PLL to lock at high frequencies. The PWRT
timer is used to provide an additional fixed 2 ms (nom-
inal) time-out to allow the PLL ample time to lock to the
incoming clock frequency.
 2003 Microchip Technology Inc.
Advance Information
DS39612A-page 29